1 /*********************************************************************
2 *
3 * Filename: toshoboe.h
4 * Version: 0.1
5 * Description: Driver for the Toshiba OBOE (or type-O)
6 * FIR Chipset.
7 * Status: Experimental.
8 * Author: James McKenzie <james@fishsoup.dhs.org>
9 * Created at: Sat May 8 12:35:27 1999
10 *
11 * Copyright (c) 1999-2000 James McKenzie, All Rights Reserved.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * Neither James McKenzie nor Cambridge University admit liability nor
19 * provide warranty for any of this software. This material is
20 * provided "AS-IS" and at no charge.
21 *
22 * Applicable Models : Libretto 100CT. and many more
23 *
24 ********************************************************************/
25
26 #ifndef TOSHOBOE_H
27 #define TOSHOBOE_H
28
29 /* Registers */
30 /*Receive and transmit task registers (read only) */
31 #define OBOE_RCVT (0x00+(self->base))
32 #define OBOE_XMTT (0x01+(self->base))
33 #define OBOE_XMTT_OFFSET 0x40
34
35 /*Page pointers to the TaskFile structure */
36 #define OBOE_TFP2 (0x02+(self->base))
37 #define OBOE_TFP0 (0x04+(self->base))
38 #define OBOE_TFP1 (0x05+(self->base))
39
40 /*Dunno */
41 #define OBOE_REG_3 (0x03+(self->base))
42
43 /*Number of tasks to use in Xmit and Recv queues */
44 #define OBOE_NTR (0x07+(self->base))
45 #define OBOE_NTR_XMIT4 0x00
46 #define OBOE_NTR_XMIT8 0x10
47 #define OBOE_NTR_XMIT16 0x30
48 #define OBOE_NTR_XMIT32 0x70
49 #define OBOE_NTR_XMIT64 0xf0
50 #define OBOE_NTR_RECV4 0x00
51 #define OBOE_NTR_RECV8 0x01
52 #define OBOE_NTR_RECV6 0x03
53 #define OBOE_NTR_RECV32 0x07
54 #define OBOE_NTR_RECV64 0x0f
55
56 /* Dunno */
57 #define OBOE_REG_9 (0x09+(self->base))
58
59 /* Interrupt Status Register */
60 #define OBOE_ISR (0x0c+(self->base))
61 #define OBOE_ISR_TXDONE 0x80
62 #define OBOE_ISR_RXDONE 0x40
63 #define OBOE_ISR_20 0x20
64 #define OBOE_ISR_10 0x10
65 #define OBOE_ISR_8 0x08 /*This is collision or parity or something */
66 #define OBOE_ISR_4 0x08
67 #define OBOE_ISR_2 0x08
68 #define OBOE_ISR_1 0x08
69
70 /*Dunno */
71 #define OBOE_REG_D (0x0d+(self->base))
72
73 /*Register Lock Register */
74 #define OBOE_LOCK ((self->base)+0x0e)
75
76
77
78 /*Speed control registers */
79 #define OBOE_PMDL (0x10+(self->base))
80 #define OBOE_PMDL_SIR 0x18
81 #define OBOE_PMDL_MIR 0xa0
82 #define OBOE_PMDL_FIR 0x40
83
84 #define OBOE_SMDL (0x18+(self->base))
85 #define OBOE_SMDL_SIR 0x20
86 #define OBOE_SMDL_MIR 0x01
87 #define OBOE_SMDL_FIR 0x0f
88
89 #define OBOE_UDIV (0x19+(self->base))
90
91 /*Dunno */
92 #define OBOE_REG_11 (0x11+(self->base))
93
94 /*Chip Reset Register */
95 #define OBOE_RST (0x15+(self->base))
96 #define OBOE_RST_WRAP 0x8
97
98 /*Dunno */
99 #define OBOE_REG_1A (0x1a+(self->base))
100 #define OBOE_REG_1B (0x1b+(self->base))
101
102 /* The PCI ID of the OBOE chip */
103 #ifndef PCI_DEVICE_ID_FIR701
104 #define PCI_DEVICE_ID_FIR701 0x0701
105 #endif
106
107 typedef unsigned int dword;
108 typedef unsigned short int word;
109 typedef unsigned char byte;
110 typedef dword Paddr;
111
112 struct OboeTask
113 {
114 __u16 len;
115 __u8 unused;
116 __u8 control;
117 __u32 buffer;
118 };
119
120 #define OBOE_NTASKS 64
121
122 struct OboeTaskFile
123 {
124 struct OboeTask recv[OBOE_NTASKS];
125 struct OboeTask xmit[OBOE_NTASKS];
126 };
127
128 #define OBOE_TASK_BUF_LEN (sizeof(struct OboeTaskFile) << 1)
129
130 /*These set the number of slots in use */
131 #define TX_SLOTS 4
132 #define RX_SLOTS 4
133
134 /* You need also to change this, toshiba uses 4,8 and 4,4 */
135 /* It makes no difference if you are only going to use ONETASK mode */
136 /* remember each buffer use XX_BUF_SZ more _PHYSICAL_ memory */
137 #define OBOE_NTR_VAL (OBOE_NTR_XMIT4 | OBOE_NTR_RECV4)
138
139 struct toshoboe_cb
140 {
141 struct net_device *netdev; /* Yes! we are some kind of netdevice */
142 struct net_device_stats stats;
143
144 struct irlap_cb *irlap; /* The link layer we are binded to */
145 struct qos_info qos; /* QoS capabilities for this device */
146
147 chipio_t io; /* IrDA controller information */
148
149 __u32 flags; /* Interface flags */
150 __u32 new_speed;
151
152 struct pci_dev *pdev; /*PCI device */
153 int base; /*IO base */
154 int txpending; /*how many tx's are pending */
155 int txs, rxs; /*Which slots are we at */
156 void *taskfilebuf; /*The unaligned taskfile buffer */
157 struct OboeTaskFile *taskfile; /*The taskfile */
158 void *xmit_bufs[TX_SLOTS]; /*The buffers */
159 void *recv_bufs[RX_SLOTS];
160 int open;
161 int stopped; /*Stopped by some or other APM stuff*/
162 };
163
164
165 #endif
166
167
168
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