1 /*********************************************************************
2 *
3 * Filename: smc-ircc.h
4 * Version: 0.3
5 * Description: Definitions for the SMC IrCC chipset
6 * Status: Experimental.
7 * Author: Thomas Davis (tadavis@jps.net)
8 *
9 * Copyright (c) 1999-2000, Dag Brattli <dagb@cs.uit.no>
10 * Copyright (c) 1998-1999, Thomas Davis (tadavis@jps.net>
11 * All Rights Reserved
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 *
28 ********************************************************************/
29
30 #ifndef SMC_IRCC_H
31 #define SMC_IRCC_H
32
33 #include <linux/spinlock.h>
34 #include <linux/pm.h>
35
36 #include <net/irda/irport.h>
37
38 /* DMA modes needed */
39 #define DMA_TX_MODE 0x08 /* Mem to I/O, ++, demand. */
40 #define DMA_RX_MODE 0x04 /* I/O to mem, ++, demand. */
41
42 /* Master Control Register */
43 #define IRCC_MASTER 0x07
44 #define IRCC_MASTER_POWERDOWN 0x80
45 #define IRCC_MASTER_RESET 0x40
46 #define IRCC_MASTER_INT_EN 0x20
47 #define IRCC_MASTER_ERROR_RESET 0x10
48
49 /* Register block 0 */
50
51 /* Interrupt Identification */
52 #define IRCC_IIR 0x01
53 #define IRCC_IIR_ACTIVE_FRAME 0x80
54 #define IRCC_IIR_EOM 0x40
55 #define IRCC_IIR_RAW_MODE 0x20
56 #define IRCC_IIR_FIFO 0x10
57
58 /* Interrupt Enable */
59 #define IRCC_IER 0x02
60 #define IRCC_IER_ACTIVE_FRAME 0x80
61 #define IRCC_IER_EOM 0x40
62 #define IRCC_IER_RAW_MODE 0x20
63 #define IRCC_IER_FIFO 0x10
64
65 /* Line Status Register */
66 #define IRCC_LSR 0x03
67 #define IRCC_LSR_UNDERRUN 0x80
68 #define IRCC_LSR_OVERRUN 0x40
69 #define IRCC_LSR_FRAME_ERROR 0x20
70 #define IRCC_LSR_SIZE_ERROR 0x10
71 #define IRCC_LSR_CRC_ERROR 0x80
72 #define IRCC_LSR_FRAME_ABORT 0x40
73
74 /* Line Control Register A */
75 #define IRCC_LCR_A 0x04
76 #define IRCC_LCR_A_FIFO_RESET 0x80
77 #define IRCC_LCR_A_FAST 0x40
78 #define IRCC_LCR_A_GP_DATA 0x20
79 #define IRCC_LCR_A_RAW_TX 0x10
80 #define IRCC_LCR_A_RAW_RX 0x08
81 #define IRCC_LCR_A_ABORT 0x04
82 #define IRCC_LCR_A_DATA_DONE 0x02
83
84 /* Line Control Register B */
85 #define IRCC_LCR_B 0x05
86 #define IRCC_LCR_B_SCE_DISABLED 0x00
87 #define IRCC_LCR_B_SCE_TRANSMIT 0x40
88 #define IRCC_LCR_B_SCE_RECEIVE 0x80
89 #define IRCC_LCR_B_SCE_UNDEFINED 0xc0
90 #define IRCC_LCR_B_SIP_ENABLE 0x20
91 #define IRCC_LCR_B_BRICK_WALL 0x10
92
93 /* Bus Status Register */
94 #define IRCC_BSR 0x06
95 #define IRCC_BSR_NOT_EMPTY 0x80
96 #define IRCC_BSR_FIFO_FULL 0x40
97 #define IRCC_BSR_TIMEOUT 0x20
98
99 /* Register block 1 */
100
101 #define IRCC_FIFO_THRESHOLD 0x02
102
103 #define IRCC_SCE_CFGA 0x00
104 #define IRCC_CFGA_AUX_IR 0x80
105 #define IRCC_CFGA_HALF_DUPLEX 0x04
106 #define IRCC_CFGA_TX_POLARITY 0x02
107 #define IRCC_CFGA_RX_POLARITY 0x01
108
109 #define IRCC_CFGA_COM 0x00
110 #define IRCC_CFGA_IRDA_SIR_A 0x08
111 #define IRCC_CFGA_ASK_SIR 0x10
112 #define IRCC_CFGA_IRDA_SIR_B 0x18
113 #define IRCC_CFGA_IRDA_HDLC 0x20
114 #define IRCC_CFGA_IRDA_4PPM 0x28
115 #define IRCC_CFGA_CONSUMER 0x30
116 #define IRCC_CFGA_RAW_IR 0x38
117 #define IRCC_CFGA_OTHER 0x40
118
119 #define IRCC_IR_HDLC 0x04
120 #define IRCC_IR_4PPM 0x01
121 #define IRCC_IR_CONSUMER 0x02
122
123 #define IRCC_SCE_CFGB 0x01
124 #define IRCC_CFGB_LOOPBACK 0x20
125 #define IRCC_CFGB_LPBCK_TX_CRC 0x10
126 #define IRCC_CFGB_NOWAIT 0x08
127 #define IRCC_CFGB_STRING_MOVE 0x04
128 #define IRCC_CFGB_DMA_BURST 0x02
129 #define IRCC_CFGB_DMA_ENABLE 0x01
130
131 #define IRCC_CFGB_MUX_COM 0x00
132 #define IRCC_CFGB_MUX_IR 0x40
133 #define IRCC_CFGB_MUX_AUX 0x80
134 #define IRCC_CFGB_MUX_INACTIVE 0xc0
135
136 /* Register block 3 - Identification Registers! */
137 #define IRCC_ID_HIGH 0x00 /* 0x10 */
138 #define IRCC_ID_LOW 0x01 /* 0xB8 */
139 #define IRCC_CHIP_ID 0x02 /* 0xF1 */
140 #define IRCC_VERSION 0x03 /* 0x01 */
141 #define IRCC_INTERFACE 0x04 /* low 4 = DMA, high 4 = IRQ */
142
143 /* Register block 4 - IrDA */
144 #define IRCC_CONTROL 0x00
145 #define IRCC_BOF_COUNT_LO 0x01 /* Low byte */
146 #define IRCC_BOF_COUNT_HI 0x00 /* High nibble (bit 0-3) */
147 #define IRCC_BRICKWALL_CNT_LO 0x02 /* Low byte */
148 #define IRCC_BRICKWALL_CNT_HI 0x03 /* High nibble (bit 4-7) */
149 #define IRCC_TX_SIZE_LO 0x04 /* Low byte */
150 #define IRCC_TX_SIZE_HI 0x03 /* High nibble (bit 0-3) */
151 #define IRCC_RX_SIZE_HI 0x05 /* High nibble (bit 0-3) */
152 #define IRCC_RX_SIZE_LO 0x06 /* Low byte */
153
154 #define IRCC_1152 0x80
155 #define IRCC_CRC 0x40
156
157 struct smc_chip {
158 char *name;
159 unsigned char entr1;
160 unsigned char entr2;
161 unsigned char cid_index;
162 unsigned char cid_value;
163 int (*probe)(struct smc_chip *chip, chipio_t *info);
164 };
165 typedef struct smc_chip smc_chip_t;
166
167 /* Private data for each instance */
168 struct ircc_cb {
169 struct net_device *netdev; /* Yes! we are some kind of netdevice */
170 struct irlap_cb *irlap; /* The link layer we are binded to */
171
172 chipio_t io; /* IrDA controller information */
173 iobuff_t tx_buff; /* Transmit buffer */
174 iobuff_t rx_buff; /* Receive buffer */
175
176 struct irport_cb *irport;
177
178 spinlock_t lock; /* For serializing operations */
179
180 __u32 new_speed;
181 __u32 flags; /* Interface flags */
182
183 int tx_buff_offsets[10]; /* Offsets between frames in tx_buff */
184 int tx_len; /* Number of frames in tx_buff */
185
186 struct pm_dev *pmdev;
187 };
188
189 #endif /* SMC_IRCC_H */
190
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