1 /*********************************************************************
2 *
3 * Filename: nsc-ircc.h
4 * Version:
5 * Description:
6 * Status: Experimental.
7 * Author: Dag Brattli <dagb@cs.uit.no>
8 * Created at: Fri Nov 13 14:37:40 1998
9 * Modified at: Sun Jan 23 17:47:00 2000
10 * Modified by: Dag Brattli <dagb@cs.uit.no>
11 *
12 * Copyright (c) 1998-2000 Dag Brattli <dagb@cs.uit.no>
13 * Copyright (c) 1998 Lichen Wang, <lwang@actisys.com>
14 * Copyright (c) 1998 Actisys Corp., www.actisys.com
15 * All Rights Reserved
16 *
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
21 *
22 * Neither Dag Brattli nor University of Tromsų admit liability nor
23 * provide warranty for any of this software. This material is
24 * provided "AS-IS" and at no charge.
25 *
26 ********************************************************************/
27
28 #ifndef NSC_IRCC_H
29 #define NSC_IRCC_H
30
31 #include <linux/time.h>
32
33 #include <linux/spinlock.h>
34 #include <linux/pm.h>
35 #include <asm/io.h>
36
37 /* DMA modes needed */
38 #define DMA_TX_MODE 0x08 /* Mem to I/O, ++, demand. */
39 #define DMA_RX_MODE 0x04 /* I/O to mem, ++, demand. */
40
41 /* Config registers for the '108 */
42 #define CFG_BAIC 0x00
43 #define CFG_CSRT 0x01
44 #define CFG_MCTL 0x02
45
46 /* Config registers for the '338 */
47 #define CFG_FER 0x00
48 #define CFG_FAR 0x01
49 #define CFG_PTR 0x02
50 #define CFG_PNP0 0x1b
51 #define CFG_PNP1 0x1c
52 #define CFG_PNP3 0x4f
53
54 /* Flags for configuration register CRF0 */
55 #define APEDCRC 0x02
56 #define ENBNKSEL 0x01
57
58 /* Set 0 */
59 #define TXD 0x00 /* Transmit data port */
60 #define RXD 0x00 /* Receive data port */
61
62 /* Register 1 */
63 #define IER 0x01 /* Interrupt Enable Register*/
64 #define IER_RXHDL_IE 0x01 /* Receiver high data level interrupt */
65 #define IER_TXLDL_IE 0x02 /* Transeiver low data level interrupt */
66 #define IER_LS_IE 0x04//* Link Status Interrupt */
67 #define IER_ETXURI 0x04 /* Tx underrun */
68 #define IER_DMA_IE 0x10 /* DMA finished interrupt */
69 #define IER_TXEMP_IE 0x20
70 #define IER_SFIF_IE 0x40 /* Frame status FIFO intr */
71 #define IER_TMR_IE 0x80 /* Timer event */
72
73 #define FCR 0x02 /* (write only) */
74 #define FCR_FIFO_EN 0x01 /* Enable FIFO's */
75 #define FCR_RXSR 0x02 /* Rx FIFO soft reset */
76 #define FCR_TXSR 0x04 /* Tx FIFO soft reset */
77 #define FCR_RXTH 0x40 /* Rx FIFO threshold (set to 16) */
78 #define FCR_TXTH 0x20 /* Tx FIFO threshold (set to 17) */
79
80 #define EIR 0x02 /* (read only) */
81 #define EIR_RXHDL_EV 0x01
82 #define EIR_TXLDL_EV 0x02
83 #define EIR_LS_EV 0x04
84 #define EIR_DMA_EV 0x10
85 #define EIR_TXEMP_EV 0x20
86 #define EIR_SFIF_EV 0x40
87 #define EIR_TMR_EV 0x80
88
89 #define LCR 0x03 /* Link control register */
90 #define LCR_WLS_8 0x03 /* 8 bits */
91
92 #define BSR 0x03 /* Bank select register */
93 #define BSR_BKSE 0x80
94 #define BANK0 LCR_WLS_8 /* Must make sure that we set 8N1 */
95 #define BANK1 0x80
96 #define BANK2 0xe0
97 #define BANK3 0xe4
98 #define BANK4 0xe8
99 #define BANK5 0xec
100 #define BANK6 0xf0
101 #define BANK7 0xf4
102
103 #define MCR 0x04 /* Mode Control Register */
104 #define MCR_MODE_MASK ~(0xd0)
105 #define MCR_UART 0x00
106 #define MCR_RESERVED 0x20
107 #define MCR_SHARP_IR 0x40
108 #define MCR_SIR 0x60
109 #define MCR_MIR 0x80
110 #define MCR_FIR 0xa0
111 #define MCR_CEIR 0xb0
112 #define MCR_IR_PLS 0x10
113 #define MCR_DMA_EN 0x04
114 #define MCR_EN_IRQ 0x08
115 #define MCR_TX_DFR 0x08
116
117 #define LSR 0x05 /* Link status register */
118 #define LSR_RXDA 0x01 /* Receiver data available */
119 #define LSR_TXRDY 0x20 /* Transmitter ready */
120 #define LSR_TXEMP 0x40 /* Transmitter empty */
121
122 #define ASCR 0x07 /* Auxillary Status and Control Register */
123 #define ASCR_RXF_TOUT 0x01 /* Rx FIFO timeout */
124 #define ASCR_FEND_INF 0x02 /* Frame end bytes in rx FIFO */
125 #define ASCR_S_EOT 0x04 /* Set end of transmission */
126 #define ASCT_RXBSY 0x20 /* Rx busy */
127 #define ASCR_TXUR 0x40 /* Transeiver underrun */
128 #define ASCR_CTE 0x80 /* Clear timer event */
129
130 /* Bank 2 */
131 #define BGDL 0x00 /* Baud Generator Divisor Port (Low Byte) */
132 #define BGDH 0x01 /* Baud Generator Divisor Port (High Byte) */
133
134 #define ECR1 0x02 /* Extended Control Register 1 */
135 #define ECR1_EXT_SL 0x01 /* Extended Mode Select */
136 #define ECR1_DMANF 0x02 /* DMA Fairness */
137 #define ECR1_DMATH 0x04 /* DMA Threshold */
138 #define ECR1_DMASWP 0x08 /* DMA Swap */
139
140 #define EXCR2 0x04
141 #define EXCR2_TFSIZ 0x01 /* Rx FIFO size = 32 */
142 #define EXCR2_RFSIZ 0x04 /* Tx FIFO size = 32 */
143
144 #define TXFLV 0x06 /* Tx FIFO level */
145 #define RXFLV 0x07 /* Rx FIFO level */
146
147 /* Bank 3 */
148 #define MID 0x00
149
150 /* Bank 4 */
151 #define TMRL 0x00 /* Timer low byte */
152 #define TMRH 0x01 /* Timer high byte */
153 #define IRCR1 0x02 /* Infrared control register 1 */
154 #define IRCR1_TMR_EN 0x01 /* Timer enable */
155
156 #define TFRLL 0x04
157 #define TFRLH 0x05
158 #define RFRLL 0x06
159 #define RFRLH 0x07
160
161 /* Bank 5 */
162 #define IRCR2 0x04 /* Infrared control register 2 */
163 #define IRCR2_MDRS 0x04 /* MIR data rate select */
164 #define IRCR2_FEND_MD 0x20 /* */
165
166 #define FRM_ST 0x05 /* Frame status FIFO */
167 #define FRM_ST_VLD 0x80 /* Frame status FIFO data valid */
168 #define FRM_ST_ERR_MSK 0x5f
169 #define FRM_ST_LOST_FR 0x40 /* Frame lost */
170 #define FRM_ST_MAX_LEN 0x10 /* Max frame len exceeded */
171 #define FRM_ST_PHY_ERR 0x08 /* Physical layer error */
172 #define FRM_ST_BAD_CRC 0x04
173 #define FRM_ST_OVR1 0x02 /* Rx FIFO overrun */
174 #define FRM_ST_OVR2 0x01 /* Frame status FIFO overrun */
175
176 #define RFLFL 0x06
177 #define RFLFH 0x07
178
179 /* Bank 6 */
180 #define IR_CFG2 0x00
181 #define IR_CFG2_DIS_CRC 0x02
182
183 /* Bank 7 */
184 #define IRM_CR 0x07 /* Infrared module control register */
185 #define IRM_CR_IRX_MSL 0x40
186 #define IRM_CR_AF_MNT 0x80 /* Automatic format */
187
188 /* NSC chip information */
189 struct nsc_chip {
190 char *name; /* Name of chipset */
191 int cfg[3]; /* Config registers */
192 u_int8_t cid_index; /* Chip identification index reg */
193 u_int8_t cid_value; /* Chip identification expected value */
194 u_int8_t cid_mask; /* Chip identification revision mask */
195
196 /* Functions for probing and initializing the specific chip */
197 int (*probe)(struct nsc_chip *chip, chipio_t *info);
198 int (*init)(struct nsc_chip *chip, chipio_t *info);
199 };
200 typedef struct nsc_chip nsc_chip_t;
201
202 /* For storing entries in the status FIFO */
203 struct st_fifo_entry {
204 int status;
205 int len;
206 };
207
208 #define MAX_TX_WINDOW 7
209 #define MAX_RX_WINDOW 7
210
211 struct st_fifo {
212 struct st_fifo_entry entries[MAX_RX_WINDOW];
213 int pending_bytes;
214 int head;
215 int tail;
216 int len;
217 };
218
219 struct frame_cb {
220 void *start; /* Start of frame in DMA mem */
221 int len; /* Lenght of frame in DMA mem */
222 };
223
224 struct tx_fifo {
225 struct frame_cb queue[MAX_TX_WINDOW]; /* Info about frames in queue */
226 int ptr; /* Currently being sent */
227 int len; /* Lenght of queue */
228 int free; /* Next free slot */
229 void *tail; /* Next free start in DMA mem */
230 };
231
232 /* Private data for each instance */
233 struct nsc_ircc_cb {
234 struct st_fifo st_fifo; /* Info about received frames */
235 struct tx_fifo tx_fifo; /* Info about frames to be transmitted */
236
237 struct net_device *netdev; /* Yes! we are some kind of netdevice */
238 struct net_device_stats stats;
239
240 struct irlap_cb *irlap; /* The link layer we are binded to */
241 struct qos_info qos; /* QoS capabilities for this device */
242
243 chipio_t io; /* IrDA controller information */
244 iobuff_t tx_buff; /* Transmit buffer */
245 iobuff_t rx_buff; /* Receive buffer */
246
247 __u8 ier; /* Interrupt enable register */
248
249 struct timeval stamp;
250 struct timeval now;
251
252 spinlock_t lock; /* For serializing operations */
253
254 __u32 flags; /* Interface flags */
255 __u32 new_speed;
256 int index; /* Instance index */
257
258 struct pm_dev *dev;
259 };
260
261 static inline void switch_bank(int iobase, int bank)
262 {
263 outb(bank, iobase+BSR);
264 }
265
266 #endif /* NSC_IRCC_H */
267
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