1 /* $Id$
2 *
3 * This file is subject to the terms and conditions of the GNU General Public
4 * License. See the file "COPYING" in the main directory of this archive
5 * for more details.
6 *
7 * Copyright (c) 1997, 1999 by Ralf Baechle
8 * Copyright (c) 1999 Silicon Graphics, Inc.
9 */
10 #ifndef _ASM_BCACHE_H
11 #define _ASM_BCACHE_H
12
13 #include <linux/config.h>
14
15 #ifdef CONFIG_BOARD_SCACHE
16
17 /* Some R4000 / R4400 / R4600 / R5000 machines may have a non-dma-coherent,
18 chipset implemented caches. On machines with other CPUs the CPU does the
19 cache thing itself. */
20 struct bcache_ops {
21 void (*bc_enable)(void);
22 void (*bc_disable)(void);
23 void (*bc_wback_inv)(unsigned long page, unsigned long size);
24 void (*bc_inv)(unsigned long page, unsigned long size);
25 };
26
27 extern void indy_sc_init(void);
28 extern void sni_pcimt_sc_init(void);
29
30 extern struct bcache_ops *bcops;
31
32 extern inline void bc_enable(void)
33 {
34 bcops->bc_enable();
35 }
36
37 extern inline void bc_disable(void)
38 {
39 bcops->bc_disable();
40 }
41
42 extern inline void bc_wback_inv(unsigned long page, unsigned long size)
43 {
44 bcops->bc_wback_inv(page, size);
45 }
46
47 extern inline void bc_inv(unsigned long page, unsigned long size)
48 {
49 bcops->bc_inv(page, size);
50 }
51
52 #else /* !defined(CONFIG_BOARD_SCACHE) */
53
54 /* Not R4000 / R4400 / R4600 / R5000. */
55
56 #define bc_enable() do { } while (0)
57 #define bc_disable() do { } while (0)
58 #define bc_wback_inv(page, size) do { } while (0)
59 #define bc_inv(page, size) do { } while (0)
60
61 #endif /* !defined(CONFIG_BOARD_SCACHE) */
62
63 #endif /* _ASM_BCACHE_H */
64
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