1 /*
2 * Exported procedures for the ATI/mach64 display driver on PowerMacs.
3 *
4 * Copyright (C) 1997 Michael AK Tesch
5 * written with much help from Jon Howell
6 *
7 * Updated for 3D RAGE PRO by Geert Uytterhoeven
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14
15 /*
16 * most of the rest of this file comes from ATI sample code
17 */
18 #ifndef REGMACH64_H
19 #define REGMACH64_H
20
21 /* NON-GUI MEMORY MAPPED Registers - expressed in BYTE offsets */
22
23 #define CRTC_H_TOTAL_DISP 0x0000 /* Dword offset 0_00 */
24 #define CRTC_H_SYNC_STRT_WID 0x0004 /* Dword offset 0_01 */
25 #define CRTC_H_SYNC_STRT 0x0004
26 #define CRTC_H_SYNC_DLY 0x0005
27 #define CRTC_H_SYNC_WID 0x0006
28
29 #define CRTC_V_TOTAL_DISP 0x0008 /* Dword offset 0_02 */
30 #define CRTC_V_TOTAL 0x0008
31 #define CRTC_V_DISP 0x000A
32 #define CRTC_V_SYNC_STRT_WID 0x000C /* Dword offset 0_03 */
33 #define CRTC_V_SYNC_STRT 0x000C
34 #define CRTC_V_SYNC_WID 0x000E
35
36 #define CRTC_VLINE_CRNT_VLINE 0x0010 /* Dword offset 0_04 */
37 #define CRTC_OFF_PITCH 0x0014 /* Dword offset 0_05 */
38 #define CRTC_OFFSET 0x0014
39 #define CRTC_PITCH 0x0016
40
41 #define CRTC_INT_CNTL 0x0018 /* Dword offset 0_06 */
42 #define CRTC_GEN_CNTL 0x001C /* Dword offset 0_07 */
43 #define CRTC_PIX_WIDTH 0x001D
44 #define CRTC_FIFO 0x001E
45 #define CRTC_EXT_DISP 0x001F
46
47 #define DSP_CONFIG 0x0020 /* Dword offset 0_08 */
48 #define DSP_ON_OFF 0x0024 /* Dword offset 0_09 */
49 #define TIMER_CONFIG 0x0028 /* Dword offset 0_0A */
50 #define MEM_BUF_CNTL 0x002C /* Dword offset 0_0B */
51 #define MEM_ADDR_CONFIG 0x0034 /* Dword offset 0_0D */
52
53 #define CRT_TRAP 0x0038 /* Dword offset 0_0E */
54
55 #define I2C_CNTL_0 0x003C /* Dword offset 0_0F */
56
57 #define OVR_CLR 0x0040 /* Dword offset 0_10 */
58 #define OVR_WID_LEFT_RIGHT 0x0044 /* Dword offset 0_11 */
59 #define OVR_WID_TOP_BOTTOM 0x0048 /* Dword offset 0_12 */
60
61 #define VGA_DSP_CONFIG 0x004C /* Dword offset 0_13 */
62 #define VGA_DSP_ON_OFF 0x0050 /* Dword offset 0_14 */
63
64 #define CUR_CLR0 0x0060 /* Dword offset 0_18 */
65 #define CUR_CLR1 0x0064 /* Dword offset 0_19 */
66 #define CUR_OFFSET 0x0068 /* Dword offset 0_1A */
67 #define CUR_HORZ_VERT_POSN 0x006C /* Dword offset 0_1B */
68 #define CUR_HORZ_VERT_OFF 0x0070 /* Dword offset 0_1C */
69
70 #define CONFIG_PANEL_LG 0x0074 /* Dword offset 0_1D */
71
72 #define GP_IO 0x0078 /* Dword offset 0_1E */
73
74 #define HW_DEBUG 0x007C /* Dword offset 0_1F */
75
76 #define SCRATCH_REG0 0x0080 /* Dword offset 0_20 */
77 #define SCRATCH_REG1 0x0084 /* Dword offset 0_21 */
78
79 #define CLOCK_CNTL 0x0090 /* Dword offset 0_24 */
80 #define CLOCK_SEL_CNTL 0x0090 /* Dword offset 0_24 */
81
82 #define CONFIG_STAT1 0x0094 /* Dword offset 0_25 */
83 #define CONFIG_STAT2 0x0098 /* Dword offset 0_26 */
84
85 #define BUS_CNTL 0x00A0 /* Dword offset 0_28 */
86
87 #define LCD_INDEX 0x00A4 /* Dword offset 0_29 */
88 #define LCD_DATA 0x00A8 /* Dword offset 0_2A */
89
90 #define EXT_MEM_CNTL 0x00AC /* Dword offset 0_2B */
91 #define MEM_CNTL 0x00B0 /* Dword offset 0_2C */
92
93 #define MEM_VGA_WP_SEL 0x00B4 /* Dword offset 0_2D */
94 #define MEM_VGA_RP_SEL 0x00B8 /* Dword offset 0_2E */
95
96 #define I2C_CNTL_1 0x00BC /* Dword offset 0_2F */
97
98 #define DAC_REGS 0x00C0 /* Dword offset 0_30 */
99 #define DAC_W_INDEX 0x00C0 /* Dword offset 0_30 */
100 #define DAC_DATA 0x00C1 /* Dword offset 0_30 */
101 #define DAC_MASK 0x00C2 /* Dword offset 0_30 */
102 #define DAC_R_INDEX 0x00C3 /* Dword offset 0_30 */
103 #define DAC_CNTL 0x00C4 /* Dword offset 0_31 */
104
105 #define EXT_DAC_REGS 0x00C8 /* Dword offset 0_32 */
106
107 #define GEN_TEST_CNTL 0x00D0 /* Dword offset 0_34 */
108
109 #define CUSTOM_MACRO_CNTL 0x00D4 /* Dword offset 0_35 */
110 #define LCD_GEN_CNTL_LG 0x00D4 /* Dword offset 0_35 */
111
112 #define POWER_MANAGEMENT_LG 0x00D8 /* Dword offset 0_36 (LG) */
113
114 #define CONFIG_CNTL 0x00DC /* Dword offset 0_37 (CT, ET, VT) */
115 #define CONFIG_CHIP_ID 0x00E0 /* Dword offset 0_38 */
116 #define CONFIG_STAT0 0x00E4 /* Dword offset 0_39 */
117 #define CRC_SIG 0x00E8 /* Dword offset 0_3A */
118
119
120 /* GUI MEMORY MAPPED Registers */
121
122 #define DST_OFF_PITCH 0x0100 /* Dword offset 0_40 */
123 #define DST_X 0x0104 /* Dword offset 0_41 */
124 #define DST_Y 0x0108 /* Dword offset 0_42 */
125 #define DST_Y_X 0x010C /* Dword offset 0_43 */
126 #define DST_WIDTH 0x0110 /* Dword offset 0_44 */
127 #define DST_HEIGHT 0x0114 /* Dword offset 0_45 */
128 #define DST_HEIGHT_WIDTH 0x0118 /* Dword offset 0_46 */
129 #define DST_X_WIDTH 0x011C /* Dword offset 0_47 */
130 #define DST_BRES_LNTH 0x0120 /* Dword offset 0_48 */
131 #define DST_BRES_ERR 0x0124 /* Dword offset 0_49 */
132 #define DST_BRES_INC 0x0128 /* Dword offset 0_4A */
133 #define DST_BRES_DEC 0x012C /* Dword offset 0_4B */
134 #define DST_CNTL 0x0130 /* Dword offset 0_4C */
135 #define DST_Y_X__ALIAS__ 0x0134 /* Dword offset 0_4D */
136 #define TRAIL_BRES_ERR 0x0138 /* Dword offset 0_4E */
137 #define TRAIL_BRES_INC 0x013C /* Dword offset 0_4F */
138 #define TRAIL_BRES_DEC 0x0140 /* Dword offset 0_50 */
139 #define LEAD_BRES_LNTH 0x0144 /* Dword offset 0_51 */
140 #define Z_OFF_PITCH 0x0148 /* Dword offset 0_52 */
141 #define Z_CNTL 0x014C /* Dword offset 0_53 */
142 #define ALPHA_TST_CNTL 0x0150 /* Dword offset 0_54 */
143 #define SECONDARY_STW_EXP 0x0158 /* Dword offset 0_56 */
144 #define SECONDARY_S_X_INC 0x015C /* Dword offset 0_57 */
145 #define SECONDARY_S_Y_INC 0x0160 /* Dword offset 0_58 */
146 #define SECONDARY_S_START 0x0164 /* Dword offset 0_59 */
147 #define SECONDARY_W_X_INC 0x0168 /* Dword offset 0_5A */
148 #define SECONDARY_W_Y_INC 0x016C /* Dword offset 0_5B */
149 #define SECONDARY_W_START 0x0170 /* Dword offset 0_5C */
150 #define SECONDARY_T_X_INC 0x0174 /* Dword offset 0_5D */
151 #define SECONDARY_T_Y_INC 0x0178 /* Dword offset 0_5E */
152 #define SECONDARY_T_START 0x017C /* Dword offset 0_5F */
153
154 #define SRC_OFF_PITCH 0x0180 /* Dword offset 0_60 */
155 #define SRC_X 0x0184 /* Dword offset 0_61 */
156 #define SRC_Y 0x0188 /* Dword offset 0_62 */
157 #define SRC_Y_X 0x018C /* Dword offset 0_63 */
158 #define SRC_WIDTH1 0x0190 /* Dword offset 0_64 */
159 #define SRC_HEIGHT1 0x0194 /* Dword offset 0_65 */
160 #define SRC_HEIGHT1_WIDTH1 0x0198 /* Dword offset 0_66 */
161 #define SRC_X_START 0x019C /* Dword offset 0_67 */
162 #define SRC_Y_START 0x01A0 /* Dword offset 0_68 */
163 #define SRC_Y_X_START 0x01A4 /* Dword offset 0_69 */
164 #define SRC_WIDTH2 0x01A8 /* Dword offset 0_6A */
165 #define SRC_HEIGHT2 0x01AC /* Dword offset 0_6B */
166 #define SRC_HEIGHT2_WIDTH2 0x01B0 /* Dword offset 0_6C */
167 #define SRC_CNTL 0x01B4 /* Dword offset 0_6D */
168
169 #define SCALE_OFF 0x01C0 /* Dword offset 0_70 */
170 #define SECONDARY_SCALE_OFF 0x01C4 /* Dword offset 0_71 */
171
172 #define TEX_0_OFF 0x01C0 /* Dword offset 0_70 */
173 #define TEX_1_OFF 0x01C4 /* Dword offset 0_71 */
174 #define TEX_2_OFF 0x01C8 /* Dword offset 0_72 */
175 #define TEX_3_OFF 0x01CC /* Dword offset 0_73 */
176 #define TEX_4_OFF 0x01D0 /* Dword offset 0_74 */
177 #define TEX_5_OFF 0x01D4 /* Dword offset 0_75 */
178 #define TEX_6_OFF 0x01D8 /* Dword offset 0_76 */
179 #define TEX_7_OFF 0x01DC /* Dword offset 0_77 */
180
181 #define SCALE_WIDTH 0x01DC /* Dword offset 0_77 */
182 #define SCALE_HEIGHT 0x01E0 /* Dword offset 0_78 */
183
184 #define TEX_8_OFF 0x01E0 /* Dword offset 0_78 */
185 #define TEX_9_OFF 0x01E4 /* Dword offset 0_79 */
186 #define TEX_10_OFF 0x01E8 /* Dword offset 0_7A */
187 #define S_Y_INC 0x01EC /* Dword offset 0_7B */
188
189 #define SCALE_PITCH 0x01EC /* Dword offset 0_7B */
190 #define SCALE_X_INC 0x01F0 /* Dword offset 0_7C */
191
192 #define RED_X_INC 0x01F0 /* Dword offset 0_7C */
193 #define GREEN_X_INC 0x01F4 /* Dword offset 0_7D */
194
195 #define SCALE_Y_INC 0x01F4 /* Dword offset 0_7D */
196 #define SCALE_VACC 0x01F8 /* Dword offset 0_7E */
197 #define SCALE_3D_CNTL 0x01FC /* Dword offset 0_7F */
198
199 #define HOST_DATA0 0x0200 /* Dword offset 0_80 */
200 #define HOST_DATA1 0x0204 /* Dword offset 0_81 */
201 #define HOST_DATA2 0x0208 /* Dword offset 0_82 */
202 #define HOST_DATA3 0x020C /* Dword offset 0_83 */
203 #define HOST_DATA4 0x0210 /* Dword offset 0_84 */
204 #define HOST_DATA5 0x0214 /* Dword offset 0_85 */
205 #define HOST_DATA6 0x0218 /* Dword offset 0_86 */
206 #define HOST_DATA7 0x021C /* Dword offset 0_87 */
207 #define HOST_DATA8 0x0220 /* Dword offset 0_88 */
208 #define HOST_DATA9 0x0224 /* Dword offset 0_89 */
209 #define HOST_DATAA 0x0228 /* Dword offset 0_8A */
210 #define HOST_DATAB 0x022C /* Dword offset 0_8B */
211 #define HOST_DATAC 0x0230 /* Dword offset 0_8C */
212 #define HOST_DATAD 0x0234 /* Dword offset 0_8D */
213 #define HOST_DATAE 0x0238 /* Dword offset 0_8E */
214 #define HOST_DATAF 0x023C /* Dword offset 0_8F */
215 #define HOST_CNTL 0x0240 /* Dword offset 0_90 */
216
217 #define BM_HOSTDATA 0x0244 /* Dword offset 0_91 */
218 #define BM_ADDR 0x0248 /* Dword offset 0_92 */
219 #define BM_DATA 0x0248 /* Dword offset 0_92 */
220 #define BM_GUI_TABLE_CMD 0x024C /* Dword offset 0_93 */
221
222 #define PAT_REG0 0x0280 /* Dword offset 0_A0 */
223 #define PAT_REG1 0x0284 /* Dword offset 0_A1 */
224 #define PAT_CNTL 0x0288 /* Dword offset 0_A2 */
225
226 #define SC_LEFT 0x02A0 /* Dword offset 0_A8 */
227 #define SC_RIGHT 0x02A4 /* Dword offset 0_A9 */
228 #define SC_LEFT_RIGHT 0x02A8 /* Dword offset 0_AA */
229 #define SC_TOP 0x02AC /* Dword offset 0_AB */
230 #define SC_BOTTOM 0x02B0 /* Dword offset 0_AC */
231 #define SC_TOP_BOTTOM 0x02B4 /* Dword offset 0_AD */
232
233 #define DP_BKGD_CLR 0x02C0 /* Dword offset 0_B0 */
234 #define DP_FOG_CLR 0x02C4 /* Dword offset 0_B1 */
235 #define DP_FRGD_CLR 0x02C4 /* Dword offset 0_B1 */
236 #define DP_WRITE_MASK 0x02C8 /* Dword offset 0_B2 */
237 #define DP_CHAIN_MASK 0x02CC /* Dword offset 0_B3 */
238 #define DP_PIX_WIDTH 0x02D0 /* Dword offset 0_B4 */
239 #define DP_MIX 0x02D4 /* Dword offset 0_B5 */
240 #define DP_SRC 0x02D8 /* Dword offset 0_B6 */
241 #define DP_FRGD_CLR_MIX 0x02DC /* Dword offset 0_B7 */
242 #define DP_FRGD_BLGD_CLR 0x02E0 /* Dword offset 0_B8 */
243
244 #define DST_X_Y 0x02E8 /* Dword offset 0_BA */
245 #define DST_WIDTH_HEIGHT 0x02EC /* Dword offset 0_BB */
246 #define USR_DST_PICTH 0x02F0 /* Dword offset 0_BC */
247 #define DP_SET_GUI_ENGINE2 0x02F8 /* Dword offset 0_BE */
248 #define DP_SET_GUI_ENGINE 0x02FC /* Dword offset 0_BF */
249
250 #define CLR_CMP_CLR 0x0300 /* Dword offset 0_C0 */
251 #define CLR_CMP_MASK 0x0304 /* Dword offset 0_C1 */
252 #define CLR_CMP_CNTL 0x0308 /* Dword offset 0_C2 */
253
254 #define FIFO_STAT 0x0310 /* Dword offset 0_C4 */
255
256 #define CONTEXT_MASK 0x0320 /* Dword offset 0_C8 */
257 #define CONTEXT_LOAD_CNTL 0x032C /* Dword offset 0_CB */
258
259 #define GUI_TRAJ_CNTL 0x0330 /* Dword offset 0_CC */
260 #define GUI_STAT 0x0338 /* Dword offset 0_CE */
261
262 #define TEX_PALETTE_INDEX 0x0340 /* Dword offset 0_D0 */
263 #define STW_EXP 0x0344 /* Dword offset 0_D1 */
264 #define LOG_MAX_INC 0x0348 /* Dword offset 0_D2 */
265 #define S_X_INC 0x034C /* Dword offset 0_D3 */
266 #define S_Y_INC__ALIAS__ 0x0350 /* Dword offset 0_D4 */
267
268 #define SCALE_PITCH__ALIAS__ 0x0350 /* Dword offset 0_D4 */
269
270 #define S_START 0x0354 /* Dword offset 0_D5 */
271 #define W_X_INC 0x0358 /* Dword offset 0_D6 */
272 #define W_Y_INC 0x035C /* Dword offset 0_D7 */
273 #define W_START 0x0360 /* Dword offset 0_D8 */
274 #define T_X_INC 0x0364 /* Dword offset 0_D9 */
275 #define T_Y_INC 0x0368 /* Dword offset 0_DA */
276
277 #define SECONDARY_SCALE_PITCH 0x0368 /* Dword offset 0_DA */
278
279 #define T_START 0x036C /* Dword offset 0_DB */
280 #define TEX_SIZE_PITCH 0x0370 /* Dword offset 0_DC */
281 #define TEX_CNTL 0x0374 /* Dword offset 0_DD */
282 #define SECONDARY_TEX_OFFSET 0x0378 /* Dword offset 0_DE */
283 #define TEX_PALETTE 0x037C /* Dword offset 0_DF */
284
285 #define SCALE_PITCH_BOTH 0x0380 /* Dword offset 0_E0 */
286 #define SECONDARY_SCALE_OFF_ACC 0x0384 /* Dword offset 0_E1 */
287 #define SCALE_OFF_ACC 0x0388 /* Dword offset 0_E2 */
288 #define SCALE_DST_Y_X 0x038C /* Dword offset 0_E3 */
289
290 #define COMPOSITE_SHADOW_ID 0x0398 /* Dword offset 0_E6 */
291
292 #define SECONDARY_SCALE_X_INC 0x039C /* Dword offset 0_E7 */
293
294 #define SPECULAR_RED_X_INC 0x039C /* Dword offset 0_E7 */
295 #define SPECULAR_RED_Y_INC 0x03A0 /* Dword offset 0_E8 */
296 #define SPECULAR_RED_START 0x03A4 /* Dword offset 0_E9 */
297
298 #define SECONDARY_SCALE_HACC 0x03A4 /* Dword offset 0_E9 */
299
300 #define SPECULAR_GREEN_X_INC 0x03A8 /* Dword offset 0_EA */
301 #define SPECULAR_GREEN_Y_INC 0x03AC /* Dword offset 0_EB */
302 #define SPECULAR_GREEN_START 0x03B0 /* Dword offset 0_EC */
303 #define SPECULAR_BLUE_X_INC 0x03B4 /* Dword offset 0_ED */
304 #define SPECULAR_BLUE_Y_INC 0x03B8 /* Dword offset 0_EE */
305 #define SPECULAR_BLUE_START 0x03BC /* Dword offset 0_EF */
306
307 #define SCALE_X_INC__ALIAS__ 0x03C0 /* Dword offset 0_F0 */
308
309 #define RED_X_INC__ALIAS__ 0x03C0 /* Dword offset 0_F0 */
310 #define RED_Y_INC 0x03C4 /* Dword offset 0_F1 */
311 #define RED_START 0x03C8 /* Dword offset 0_F2 */
312
313 #define SCALE_HACC 0x03C8 /* Dword offset 0_F2 */
314 #define SCALE_Y_INC__ALIAS__ 0x03CC /* Dword offset 0_F3 */
315
316 #define GREEN_X_INC__ALIAS__ 0x03CC /* Dword offset 0_F3 */
317 #define GREEN_Y_INC 0x03D0 /* Dword offset 0_F4 */
318
319 #define SECONDARY_SCALE_Y_INC 0x03D0 /* Dword offset 0_F4 */
320 #define SECONDARY_SCALE_VACC 0x03D4 /* Dword offset 0_F5 */
321
322 #define GREEN_START 0x03D4 /* Dword offset 0_F5 */
323 #define BLUE_X_INC 0x03D8 /* Dword offset 0_F6 */
324 #define BLUE_Y_INC 0x03DC /* Dword offset 0_F7 */
325 #define BLUE_START 0x03E0 /* Dword offset 0_F8 */
326 #define Z_X_INC 0x03E4 /* Dword offset 0_F9 */
327 #define Z_Y_INC 0x03E8 /* Dword offset 0_FA */
328 #define Z_START 0x03EC /* Dword offset 0_FB */
329 #define ALPHA_X_INC 0x03F0 /* Dword offset 0_FC */
330 #define FOG_X_INC 0x03F0 /* Dword offset 0_FC */
331 #define ALPHA_Y_INC 0x03F4 /* Dword offset 0_FD */
332 #define FOG_Y_INC 0x03F4 /* Dword offset 0_FD */
333 #define ALPHA_START 0x03F8 /* Dword offset 0_FE */
334 #define FOG_START 0x03F8 /* Dword offset 0_FE */
335
336 #define OVERLAY_Y_X_START 0x0400 /* Dword offset 1_00 */
337 #define OVERLAY_Y_X_END 0x0404 /* Dword offset 1_01 */
338 #define OVERLAY_VIDEO_KEY_CLR 0x0408 /* Dword offset 1_02 */
339 #define OVERLAY_VIDEO_KEY_MSK 0x040C /* Dword offset 1_03 */
340 #define OVERLAY_GRAPHICS_KEY_CLR 0x0410 /* Dword offset 1_04 */
341 #define OVERLAY_GRAPHICS_KEY_MSK 0x0414 /* Dword offset 1_05 */
342 #define OVERLAY_KEY_CNTL 0x0418 /* Dword offset 1_06 */
343
344 #define OVERLAY_SCALE_INC 0x0420 /* Dword offset 1_08 */
345 #define OVERLAY_SCALE_CNTL 0x0424 /* Dword offset 1_09 */
346 #define SCALER_HEIGHT_WIDTH 0x0428 /* Dword offset 1_0A */
347 #define SCALER_TEST 0x042C /* Dword offset 1_0B */
348 #define SCALER_BUF0_OFFSET 0x0434 /* Dword offset 1_0D */
349 #define SCALER_BUF1_OFFSET 0x0438 /* Dword offset 1_0E */
350 #define SCALE_BUF_PITCH 0x043C /* Dword offset 1_0F */
351
352 #define CAPTURE_START_END 0x0440 /* Dword offset 1_10 */
353 #define CAPTURE_X_WIDTH 0x0444 /* Dword offset 1_11 */
354 #define VIDEO_FORMAT 0x0448 /* Dword offset 1_12 */
355 #define VBI_START_END 0x044C /* Dword offset 1_13 */
356 #define CAPTURE_CONFIG 0x0450 /* Dword offset 1_14 */
357 #define TRIG_CNTL 0x0454 /* Dword offset 1_15 */
358
359 #define OVERLAY_EXCLUSIVE_HORZ 0x0458 /* Dword offset 1_16 */
360 #define OVERLAY_EXCLUSIVE_VERT 0x045C /* Dword offset 1_17 */
361
362 #define VAL_WIDTH 0x0460 /* Dword offset 1_18 */
363 #define CAPTURE_DEBUG 0x0464 /* Dword offset 1_19 */
364 #define VIDEO_SYNC_TEST 0x0468 /* Dword offset 1_1A */
365
366 #define SNAPSHOT_VH_COUNTS 0x0470 /* Dword offset 1_1C */
367 #define SNAPSHOT_F_COUNT 0x0474 /* Dword offset 1_1D */
368 #define N_VIF_COUNT 0x0478 /* Dword offset 1_1E */
369 #define SNAPSHOT_VIF_COUNT 0x047C /* Dword offset 1_1F */
370
371 #define CAPTURE_BUF0_OFFSET 0x0480 /* Dword offset 1_20 */
372 #define CAPTURE_BUF1_OFFSET 0x0484 /* Dword offset 1_21 */
373 #define CAPTURE_BUF_PITCH 0x0488 /* Dword offset 1_22 */
374
375 #define MPP_CONFIG 0x04C0 /* Dword offset 1_30 */
376 #define MPP_STROBE_SEQ 0x04C4 /* Dword offset 1_31 */
377 #define MPP_ADDR 0x04C8 /* Dword offset 1_32 */
378 #define MPP_DATA 0x04CC /* Dword offset 1_33 */
379 #define TVO_CNTL 0x0500 /* Dword offset 1_40 */
380
381 #define CRT_HORZ_VERT_LOAD 0x0544 /* Dword offset 1_51 */
382
383 #define AGP_BASE 0x0548 /* Dword offset 1_52 */
384 #define AGP_CNTL 0x054C /* Dword offset 1_53 */
385
386 #define SCALER_COLOUR_CNTL 0x0550 /* Dword offset 1_54 */
387 #define SCALER_H_COEFF0 0x0554 /* Dword offset 1_55 */
388 #define SCALER_H_COEFF1 0x0558 /* Dword offset 1_56 */
389 #define SCALER_H_COEFF2 0x055C /* Dword offset 1_57 */
390 #define SCALER_H_COEFF3 0x0560 /* Dword offset 1_58 */
391 #define SCALER_H_COEFF4 0x0564 /* Dword offset 1_59 */
392
393 #define GUI_CNTL 0x0578 /* Dword offset 1_5E */
394
395 #define BM_FRAME_BUF_OFFSET 0x0580 /* Dword offset 1_60 */
396 #define BM_SYSTEM_MEM_ADDR 0x0584 /* Dword offset 1_61 */
397 #define BM_COMMAND 0x0588 /* Dword offset 1_62 */
398 #define BM_STATUS 0x058C /* Dword offset 1_63 */
399 #define BM_GUI_TABLE 0x05B8 /* Dword offset 1_6E */
400 #define BM_SYSTEM_TABLE 0x05BC /* Dword offset 1_6F */
401
402 #define SCALER_BUF0_OFFSET_U 0x05D4 /* Dword offset 1_75 */
403 #define SCALER_BUF0_OFFSET_V 0x05D8 /* Dword offset 1_76 */
404 #define SCALER_BUF1_OFFSET_U 0x05DC /* Dword offset 1_77 */
405 #define SCALER_BUF1_OFFSET_V 0x05E0 /* Dword offset 1_78 */
406
407 #define VERTEX_1_S 0x0640 /* Dword offset 1_90 */
408 #define VERTEX_1_T 0x0644 /* Dword offset 1_91 */
409 #define VERTEX_1_W 0x0648 /* Dword offset 1_92 */
410 #define VERTEX_1_SPEC_ARGB 0x064C /* Dword offset 1_93 */
411 #define VERTEX_1_Z 0x0650 /* Dword offset 1_94 */
412 #define VERTEX_1_ARGB 0x0654 /* Dword offset 1_95 */
413 #define VERTEX_1_X_Y 0x0658 /* Dword offset 1_96 */
414 #define ONE_OVER_AREA 0x065C /* Dword offset 1_97 */
415 #define VERTEX_2_S 0x0660 /* Dword offset 1_98 */
416 #define VERTEX_2_T 0x0664 /* Dword offset 1_99 */
417 #define VERTEX_2_W 0x0668 /* Dword offset 1_9A */
418 #define VERTEX_2_SPEC_ARGB 0x066C /* Dword offset 1_9B */
419 #define VERTEX_2_Z 0x0670 /* Dword offset 1_9C */
420 #define VERTEX_2_ARGB 0x0674 /* Dword offset 1_9D */
421 #define VERTEX_2_X_Y 0x0678 /* Dword offset 1_9E */
422 #define ONE_OVER_AREA 0x065C /* Dword offset 1_9F */
423 #define VERTEX_3_S 0x0680 /* Dword offset 1_A0 */
424 #define VERTEX_3_T 0x0684 /* Dword offset 1_A1 */
425 #define VERTEX_3_W 0x0688 /* Dword offset 1_A2 */
426 #define VERTEX_3_SPEC_ARGB 0x068C /* Dword offset 1_A3 */
427 #define VERTEX_3_Z 0x0690 /* Dword offset 1_A4 */
428 #define VERTEX_3_ARGB 0x0694 /* Dword offset 1_A5 */
429 #define VERTEX_3_X_Y 0x0698 /* Dword offset 1_A6 */
430 #define ONE_OVER_AREA 0x065C /* Dword offset 1_A7 */
431 #define VERTEX_1_S 0x0640 /* Dword offset 1_AB */
432 #define VERTEX_1_T 0x0644 /* Dword offset 1_AC */
433 #define VERTEX_1_W 0x0648 /* Dword offset 1_AD */
434 #define VERTEX_2_S 0x0660 /* Dword offset 1_AE */
435 #define VERTEX_2_T 0x0664 /* Dword offset 1_AF */
436 #define VERTEX_2_W 0x0668 /* Dword offset 1_B0 */
437 #define VERTEX_3_SECONDARY_S 0x06C0 /* Dword offset 1_B0 */
438 #define VERTEX_3_S 0x0680 /* Dword offset 1_B1 */
439 #define VERTEX_3_SECONDARY_T 0x06C4 /* Dword offset 1_B1 */
440 #define VERTEX_3_T 0x0684 /* Dword offset 1_B2 */
441 #define VERTEX_3_SECONDARY_W 0x06C8 /* Dword offset 1_B2 */
442 #define VERTEX_3_W 0x0688 /* Dword offset 1_B3 */
443 #define VERTEX_1_SPEC_ARGB 0x064C /* Dword offset 1_B4 */
444 #define VERTEX_2_SPEC_ARGB 0x066C /* Dword offset 1_B5 */
445 #define VERTEX_3_SPEC_ARGB 0x068C /* Dword offset 1_B6 */
446 #define VERTEX_1_Z 0x0650 /* Dword offset 1_B7 */
447 #define VERTEX_2_Z 0x0670 /* Dword offset 1_B8 */
448 #define VERTEX_3_Z 0x0690 /* Dword offset 1_B9 */
449 #define VERTEX_1_ARGB 0x0654 /* Dword offset 1_BA */
450 #define VERTEX_2_ARGB 0x0674 /* Dword offset 1_BB */
451 #define VERTEX_3_ARGB 0x0694 /* Dword offset 1_BC */
452 #define VERTEX_1_X_Y 0x0658 /* Dword offset 1_BD */
453 #define VERTEX_2_X_Y 0x0678 /* Dword offset 1_BE */
454 #define VERTEX_3_X_Y 0x0698 /* Dword offset 1_BF */
455 #define ONE_OVER_AREA_UC 0x0700 /* Dword offset 1_C0 */
456 #define SETUP_CNTL 0x0704 /* Dword offset 1_C1 */
457 #define VERTEX_1_SECONDARY_S 0x0728 /* Dword offset 1_CA */
458 #define VERTEX_1_SECONDARY_T 0x072C /* Dword offset 1_CB */
459 #define VERTEX_1_SECONDARY_W 0x0730 /* Dword offset 1_CC */
460 #define VERTEX_2_SECONDARY_S 0x0734 /* Dword offset 1_CD */
461 #define VERTEX_2_SECONDARY_T 0x0738 /* Dword offset 1_CE */
462 #define VERTEX_2_SECONDARY_W 0x073C /* Dword offset 1_CF */
463
464 #define GTC_3D_RESET_DELAY 3 /* 3D engine reset delay in ms */
465
466 /* CRTC control values (mostly CRTC_GEN_CNTL) */
467
468 #define CRTC_H_SYNC_NEG 0x00200000
469 #define CRTC_V_SYNC_NEG 0x00200000
470
471 #define CRTC_DBL_SCAN_EN 0x00000001
472 #define CRTC_INTERLACE_EN 0x00000002
473 #define CRTC_HSYNC_DIS 0x00000004
474 #define CRTC_VSYNC_DIS 0x00000008
475 #define CRTC_CSYNC_EN 0x00000010
476 #define CRTC_PIX_BY_2_EN 0x00000020 /* unused on RAGE */
477 #define CRTC_DISPLAY_DIS 0x00000040
478 #define CRTC_VGA_XOVERSCAN 0x00000040
479
480 #define CRTC_PIX_WIDTH_MASK 0x00000700
481 #define CRTC_PIX_WIDTH_4BPP 0x00000100
482 #define CRTC_PIX_WIDTH_8BPP 0x00000200
483 #define CRTC_PIX_WIDTH_15BPP 0x00000300
484 #define CRTC_PIX_WIDTH_16BPP 0x00000400
485 #define CRTC_PIX_WIDTH_24BPP 0x00000500
486 #define CRTC_PIX_WIDTH_32BPP 0x00000600
487
488 #define CRTC_BYTE_PIX_ORDER 0x00000800
489 #define CRTC_PIX_ORDER_MSN_LSN 0x00000000
490 #define CRTC_PIX_ORDER_LSN_MSN 0x00000800
491
492 #define CRTC_FIFO_LWM 0x000f0000
493
494 #define VGA_128KAP_PAGING 0x00100000
495 #define VFC_SYNC_TRISTATE 0x00200000
496 #define CRTC_LOCK_REGS 0x00400000
497 #define CRTC_SYNC_TRISTATE 0x00800000
498
499 #define CRTC_EXT_DISP_EN 0x01000000
500 #define CRTC_ENABLE 0x02000000
501 #define CRTC_DISP_REQ_ENB 0x04000000
502 #define VGA_ATI_LINEAR 0x08000000
503 #define CRTC_VSYNC_FALL_EDGE 0x10000000
504 #define VGA_TEXT_132 0x20000000
505 #define VGA_XCRT_CNT_EN 0x40000000
506 #define VGA_CUR_B_TEST 0x80000000
507
508 #define CRTC_CRNT_VLINE 0x07f00000
509 #define CRTC_VBLANK 0x00000001
510
511
512 /* DAC control values */
513
514 #define DAC_EXT_SEL_RS2 0x01
515 #define DAC_EXT_SEL_RS3 0x02
516 #define DAC_8BIT_EN 0x00000100
517 #define DAC_PIX_DLY_MASK 0x00000600
518 #define DAC_PIX_DLY_0NS 0x00000000
519 #define DAC_PIX_DLY_2NS 0x00000200
520 #define DAC_PIX_DLY_4NS 0x00000400
521 #define DAC_BLANK_ADJ_MASK 0x00001800
522 #define DAC_BLANK_ADJ_0 0x00000000
523 #define DAC_BLANK_ADJ_1 0x00000800
524 #define DAC_BLANK_ADJ_2 0x00001000
525
526
527 /* Mix control values */
528
529 #define MIX_NOT_DST 0x0000
530 #define MIX_0 0x0001
531 #define MIX_1 0x0002
532 #define MIX_DST 0x0003
533 #define MIX_NOT_SRC 0x0004
534 #define MIX_XOR 0x0005
535 #define MIX_XNOR 0x0006
536 #define MIX_SRC 0x0007
537 #define MIX_NAND 0x0008
538 #define MIX_NOT_SRC_OR_DST 0x0009
539 #define MIX_SRC_OR_NOT_DST 0x000a
540 #define MIX_OR 0x000b
541 #define MIX_AND 0x000c
542 #define MIX_SRC_AND_NOT_DST 0x000d
543 #define MIX_NOT_SRC_AND_DST 0x000e
544 #define MIX_NOR 0x000f
545
546 /* Maximum engine dimensions */
547 #define ENGINE_MIN_X 0
548 #define ENGINE_MIN_Y 0
549 #define ENGINE_MAX_X 4095
550 #define ENGINE_MAX_Y 16383
551
552 /* Mach64 engine bit constants - these are typically ORed together */
553
554 /* BUS_CNTL register constants */
555 #define BUS_FIFO_ERR_ACK 0x00200000
556 #define BUS_HOST_ERR_ACK 0x00800000
557
558 /* GEN_TEST_CNTL register constants */
559 #define GEN_OVR_OUTPUT_EN 0x20
560 #define HWCURSOR_ENABLE 0x80
561 #define GUI_ENGINE_ENABLE 0x100
562 #define BLOCK_WRITE_ENABLE 0x200
563
564 /* DSP_CONFIG register constants */
565 #define DSP_XCLKS_PER_QW 0x00003fff
566 #define DSP_LOOP_LATENCY 0x000f0000
567 #define DSP_PRECISION 0x00700000
568
569 /* DSP_ON_OFF register constants */
570 #define DSP_OFF 0x000007ff
571 #define DSP_ON 0x07ff0000
572
573 /* CLOCK_CNTL register constants */
574 #define CLOCK_SEL 0x0f
575 #define CLOCK_DIV 0x30
576 #define CLOCK_DIV1 0x00
577 #define CLOCK_DIV2 0x10
578 #define CLOCK_DIV4 0x20
579 #define CLOCK_STROBE 0x40
580 #define PLL_WR_EN 0x02
581
582 /* PLL registers */
583 #define MPLL_CNTL 0x00
584 #define VPLL_CNTL 0x01
585 #define PLL_REF_DIV 0x02
586 #define PLL_GEN_CNTL 0x03
587 #define MCLK_FB_DIV 0x04
588 #define PLL_VCLK_CNTL 0x05
589 #define VCLK_POST_DIV 0x06
590 #define VCLK0_FB_DIV 0x07
591 #define VCLK1_FB_DIV 0x08
592 #define VCLK2_FB_DIV 0x09
593 #define VCLK3_FB_DIV 0x0A
594 #define PLL_EXT_CNTL 0x0B
595 #define DLL_CNTL 0x0C
596 #define VFC_CNTL 0x0D
597 #define PLL_TEST_CTRL 0x0E
598 #define PLL_TEST_COUNT 0x0F
599
600 /* Fields in PLL registers */
601 #define PLL_PC_GAIN 0x07
602 #define PLL_VC_GAIN 0x18
603 #define PLL_DUTY_CYC 0xE0
604 #define PLL_OVERRIDE 0x01
605 #define PLL_MCLK_RST 0x02
606 #define OSC_EN 0x04
607 #define EXT_CLK_EN 0x08
608 #define MCLK_SRC_SEL 0x70
609 #define EXT_CLK_CNTL 0x80
610 #define VCLK_SRC_SEL 0x03
611 #define PLL_VCLK_RST 0x04
612 #define VCLK_INVERT 0x08
613 #define VCLK0_POST 0x03
614 #define VCLK1_POST 0x0C
615 #define VCLK2_POST 0x30
616 #define VCLK3_POST 0xC0
617
618 /* CONFIG_CNTL register constants */
619 #define APERTURE_4M_ENABLE 1
620 #define APERTURE_8M_ENABLE 2
621 #define VGA_APERTURE_ENABLE 4
622
623 /* CONFIG_STAT0 register constants (GX, CX) */
624 #define CFG_BUS_TYPE 0x00000007
625 #define CFG_MEM_TYPE 0x00000038
626 #define CFG_INIT_DAC_TYPE 0x00000e00
627
628 /* CONFIG_STAT0 register constants (CT, ET, VT) */
629 #define CFG_MEM_TYPE_xT 0x00000007
630
631 #define ISA 0
632 #define EISA 1
633 #define LOCAL_BUS 6
634 #define PCI 7
635
636 /* Memory types for GX, CX */
637 #define DRAMx4 0
638 #define VRAMx16 1
639 #define VRAMx16ssr 2
640 #define DRAMx16 3
641 #define GraphicsDRAMx16 4
642 #define EnhancedVRAMx16 5
643 #define EnhancedVRAMx16ssr 6
644
645 /* Memory types for CT, ET, VT, GT */
646 #define DRAM 1
647 #define EDO 2
648 #define PSEUDO_EDO 3
649 #define SDRAM 4
650 #define SGRAM 5
651 #define WRAM 6
652
653 #define DAC_INTERNAL 0x00
654 #define DAC_IBMRGB514 0x01
655 #define DAC_ATI68875 0x02
656 #define DAC_TVP3026_A 0x72
657 #define DAC_BT476 0x03
658 #define DAC_BT481 0x04
659 #define DAC_ATT20C491 0x14
660 #define DAC_SC15026 0x24
661 #define DAC_MU9C1880 0x34
662 #define DAC_IMSG174 0x44
663 #define DAC_ATI68860_B 0x05
664 #define DAC_ATI68860_C 0x15
665 #define DAC_TVP3026_B 0x75
666 #define DAC_STG1700 0x06
667 #define DAC_ATT498 0x16
668 #define DAC_STG1702 0x07
669 #define DAC_SC15021 0x17
670 #define DAC_ATT21C498 0x27
671 #define DAC_STG1703 0x37
672 #define DAC_CH8398 0x47
673 #define DAC_ATT20C408 0x57
674
675 #define CLK_ATI18818_0 0
676 #define CLK_ATI18818_1 1
677 #define CLK_STG1703 2
678 #define CLK_CH8398 3
679 #define CLK_INTERNAL 4
680 #define CLK_ATT20C408 5
681 #define CLK_IBMRGB514 6
682
683 /* MEM_CNTL register constants */
684 #define MEM_SIZE_ALIAS 0x00000007
685 #define MEM_SIZE_512K 0x00000000
686 #define MEM_SIZE_1M 0x00000001
687 #define MEM_SIZE_2M 0x00000002
688 #define MEM_SIZE_4M 0x00000003
689 #define MEM_SIZE_6M 0x00000004
690 #define MEM_SIZE_8M 0x00000005
691 #define MEM_SIZE_ALIAS_GTB 0x0000000F
692 #define MEM_SIZE_2M_GTB 0x00000003
693 #define MEM_SIZE_4M_GTB 0x00000007
694 #define MEM_SIZE_6M_GTB 0x00000009
695 #define MEM_SIZE_8M_GTB 0x0000000B
696 #define MEM_BNDRY 0x00030000
697 #define MEM_BNDRY_0K 0x00000000
698 #define MEM_BNDRY_256K 0x00010000
699 #define MEM_BNDRY_512K 0x00020000
700 #define MEM_BNDRY_1M 0x00030000
701 #define MEM_BNDRY_EN 0x00040000
702
703 /* ATI PCI constants */
704 #define PCI_ATI_VENDOR_ID 0x1002
705
706
707 /* CONFIG_CHIP_ID register constants */
708 #define CFG_CHIP_TYPE 0x0000FFFF
709 #define CFG_CHIP_CLASS 0x00FF0000
710 #define CFG_CHIP_REV 0xFF000000
711 #define CFG_CHIP_MAJOR 0x07000000
712 #define CFG_CHIP_FND_ID 0x38000000
713 #define CFG_CHIP_MINOR 0xC0000000
714
715
716 /* Chip IDs read from CONFIG_CHIP_ID */
717
718 /* mach64GX family */
719 #define GX_CHIP_ID 0xD7 /* mach64GX (ATI888GX00) */
720 #define CX_CHIP_ID 0x57 /* mach64CX (ATI888CX00) */
721
722 #define GX_PCI_ID 0x4758 /* mach64GX (ATI888GX00) */
723 #define CX_PCI_ID 0x4358 /* mach64CX (ATI888CX00) */
724
725 /* mach64CT family */
726 #define CT_CHIP_ID 0x4354 /* mach64CT (ATI264CT) */
727 #define ET_CHIP_ID 0x4554 /* mach64ET (ATI264ET) */
728
729 /* mach64CT family / mach64VT class */
730 #define VT_CHIP_ID 0x5654 /* mach64VT (ATI264VT) */
731 #define VU_CHIP_ID 0x5655 /* mach64VTB (ATI264VTB) */
732 #define VV_CHIP_ID 0x5656 /* mach64VT4 (ATI264VT4) */
733
734 /* mach64CT family / mach64GT (3D RAGE) class */
735 #define LB_CHIP_ID 0x4c42 /* RAGE LT PRO, AGP */
736 #define LD_CHIP_ID 0x4c44 /* RAGE LT PRO */
737 #define LG_CHIP_ID 0x4c47 /* RAGE LT */
738 #define LI_CHIP_ID 0x4c49 /* RAGE LT PRO */
739 #define LP_CHIP_ID 0x4c50 /* RAGE LT PRO */
740 #define LT_CHIP_ID 0x4c54 /* RAGE LT */
741 #define GT_CHIP_ID 0x4754 /* RAGE (GT) */
742 #define GU_CHIP_ID 0x4755 /* RAGE II/II+ (GTB) */
743 #define GV_CHIP_ID 0x4756 /* RAGE IIC, PCI */
744 #define GW_CHIP_ID 0x4757 /* RAGE IIC, AGP */
745 #define GZ_CHIP_ID 0x475a /* RAGE IIC, AGP */
746 #define GB_CHIP_ID 0x4742 /* RAGE PRO, BGA, AGP 1x and 2x */
747 #define GD_CHIP_ID 0x4744 /* RAGE PRO, BGA, AGP 1x only */
748 #define GI_CHIP_ID 0x4749 /* RAGE PRO, BGA, PCI33 only */
749 #define GP_CHIP_ID 0x4750 /* RAGE PRO, PQFP, PCI33, full 3D */
750 #define GQ_CHIP_ID 0x4751 /* RAGE PRO, PQFP, PCI33, limited 3D */
751 #define LM_CHIP_ID 0x4c4d /* RAGE Mobility PCI */
752 #define LN_CHIP_ID 0x4c4e /* RAGE Mobility AGP */
753
754
755 /* Mach64 major ASIC revisions */
756 #define MACH64_ASIC_NEC_VT_A3 0x08
757 #define MACH64_ASIC_NEC_VT_A4 0x48
758 #define MACH64_ASIC_SGS_VT_A4 0x40
759 #define MACH64_ASIC_SGS_VT_B1S1 0x01
760 #define MACH64_ASIC_SGS_GT_B1S1 0x01
761 #define MACH64_ASIC_SGS_GT_B1S2 0x41
762 #define MACH64_ASIC_UMC_GT_B2U1 0x1a
763 #define MACH64_ASIC_UMC_GT_B2U2 0x5a
764 #define MACH64_ASIC_UMC_VT_B2U3 0x9a
765 #define MACH64_ASIC_UMC_GT_B2U3 0x9a
766 #define MACH64_ASIC_UMC_R3B_D_P_A1 0x1b
767 #define MACH64_ASIC_UMC_R3B_D_P_A2 0x5b
768 #define MACH64_ASIC_UMC_R3B_D_P_A3 0x1c
769 #define MACH64_ASIC_UMC_R3B_D_P_A4 0x5c
770
771 /* Mach64 foundries */
772 #define MACH64_FND_SGS 0
773 #define MACH64_FND_NEC 1
774 #define MACH64_FND_UMC 3
775
776 /* Mach64 chip types */
777 #define MACH64_UNKNOWN 0
778 #define MACH64_GX 1
779 #define MACH64_CX 2
780 #define MACH64_CT 3
781 #define MACH64_ET 4
782 #define MACH64_VT 5
783 #define MACH64_GT 6
784
785 /* DST_CNTL register constants */
786 #define DST_X_RIGHT_TO_LEFT 0
787 #define DST_X_LEFT_TO_RIGHT 1
788 #define DST_Y_BOTTOM_TO_TOP 0
789 #define DST_Y_TOP_TO_BOTTOM 2
790 #define DST_X_MAJOR 0
791 #define DST_Y_MAJOR 4
792 #define DST_X_TILE 8
793 #define DST_Y_TILE 0x10
794 #define DST_LAST_PEL 0x20
795 #define DST_POLYGON_ENABLE 0x40
796 #define DST_24_ROTATION_ENABLE 0x80
797
798 /* SRC_CNTL register constants */
799 #define SRC_PATTERN_ENABLE 1
800 #define SRC_ROTATION_ENABLE 2
801 #define SRC_LINEAR_ENABLE 4
802 #define SRC_BYTE_ALIGN 8
803 #define SRC_LINE_X_RIGHT_TO_LEFT 0
804 #define SRC_LINE_X_LEFT_TO_RIGHT 0x10
805
806 /* HOST_CNTL register constants */
807 #define HOST_BYTE_ALIGN 1
808
809 /* GUI_TRAJ_CNTL register constants */
810 #define PAT_MONO_8x8_ENABLE 0x01000000
811 #define PAT_CLR_4x2_ENABLE 0x02000000
812 #define PAT_CLR_8x1_ENABLE 0x04000000
813
814 /* DP_CHAIN_MASK register constants */
815 #define DP_CHAIN_4BPP 0x8888
816 #define DP_CHAIN_7BPP 0xD2D2
817 #define DP_CHAIN_8BPP 0x8080
818 #define DP_CHAIN_8BPP_RGB 0x9292
819 #define DP_CHAIN_15BPP 0x4210
820 #define DP_CHAIN_16BPP 0x8410
821 #define DP_CHAIN_24BPP 0x8080
822 #define DP_CHAIN_32BPP 0x8080
823
824 /* DP_PIX_WIDTH register constants */
825 #define DST_1BPP 0
826 #define DST_4BPP 1
827 #define DST_8BPP 2
828 #define DST_15BPP 3
829 #define DST_16BPP 4
830 #define DST_32BPP 6
831 #define SRC_1BPP 0
832 #define SRC_4BPP 0x100
833 #define SRC_8BPP 0x200
834 #define SRC_15BPP 0x300
835 #define SRC_16BPP 0x400
836 #define SRC_32BPP 0x600
837 #define HOST_1BPP 0
838 #define HOST_4BPP 0x10000
839 #define HOST_8BPP 0x20000
840 #define HOST_15BPP 0x30000
841 #define HOST_16BPP 0x40000
842 #define HOST_32BPP 0x60000
843 #define BYTE_ORDER_MSB_TO_LSB 0
844 #define BYTE_ORDER_LSB_TO_MSB 0x1000000
845
846 /* DP_MIX register constants */
847 #define BKGD_MIX_NOT_D 0
848 #define BKGD_MIX_ZERO 1
849 #define BKGD_MIX_ONE 2
850 #define BKGD_MIX_D 3
851 #define BKGD_MIX_NOT_S 4
852 #define BKGD_MIX_D_XOR_S 5
853 #define BKGD_MIX_NOT_D_XOR_S 6
854 #define BKGD_MIX_S 7
855 #define BKGD_MIX_NOT_D_OR_NOT_S 8
856 #define BKGD_MIX_D_OR_NOT_S 9
857 #define BKGD_MIX_NOT_D_OR_S 10
858 #define BKGD_MIX_D_OR_S 11
859 #define BKGD_MIX_D_AND_S 12
860 #define BKGD_MIX_NOT_D_AND_S 13
861 #define BKGD_MIX_D_AND_NOT_S 14
862 #define BKGD_MIX_NOT_D_AND_NOT_S 15
863 #define BKGD_MIX_D_PLUS_S_DIV2 0x17
864 #define FRGD_MIX_NOT_D 0
865 #define FRGD_MIX_ZERO 0x10000
866 #define FRGD_MIX_ONE 0x20000
867 #define FRGD_MIX_D 0x30000
868 #define FRGD_MIX_NOT_S 0x40000
869 #define FRGD_MIX_D_XOR_S 0x50000
870 #define FRGD_MIX_NOT_D_XOR_S 0x60000
871 #define FRGD_MIX_S 0x70000
872 #define FRGD_MIX_NOT_D_OR_NOT_S 0x80000
873 #define FRGD_MIX_D_OR_NOT_S 0x90000
874 #define FRGD_MIX_NOT_D_OR_S 0xa0000
875 #define FRGD_MIX_D_OR_S 0xb0000
876 #define FRGD_MIX_D_AND_S 0xc0000
877 #define FRGD_MIX_NOT_D_AND_S 0xd0000
878 #define FRGD_MIX_D_AND_NOT_S 0xe0000
879 #define FRGD_MIX_NOT_D_AND_NOT_S 0xf0000
880 #define FRGD_MIX_D_PLUS_S_DIV2 0x170000
881
882 /* DP_SRC register constants */
883 #define BKGD_SRC_BKGD_CLR 0
884 #define BKGD_SRC_FRGD_CLR 1
885 #define BKGD_SRC_HOST 2
886 #define BKGD_SRC_BLIT 3
887 #define BKGD_SRC_PATTERN 4
888 #define FRGD_SRC_BKGD_CLR 0
889 #define FRGD_SRC_FRGD_CLR 0x100
890 #define FRGD_SRC_HOST 0x200
891 #define FRGD_SRC_BLIT 0x300
892 #define FRGD_SRC_PATTERN 0x400
893 #define MONO_SRC_ONE 0
894 #define MONO_SRC_PATTERN 0x10000
895 #define MONO_SRC_HOST 0x20000
896 #define MONO_SRC_BLIT 0x30000
897
898 /* CLR_CMP_CNTL register constants */
899 #define COMPARE_FALSE 0
900 #define COMPARE_TRUE 1
901 #define COMPARE_NOT_EQUAL 4
902 #define COMPARE_EQUAL 5
903 #define COMPARE_DESTINATION 0
904 #define COMPARE_SOURCE 0x1000000
905
906 /* FIFO_STAT register constants */
907 #define FIFO_ERR 0x80000000
908
909 /* CONTEXT_LOAD_CNTL constants */
910 #define CONTEXT_NO_LOAD 0
911 #define CONTEXT_LOAD 0x10000
912 #define CONTEXT_LOAD_AND_DO_FILL 0x20000
913 #define CONTEXT_LOAD_AND_DO_LINE 0x30000
914 #define CONTEXT_EXECUTE 0
915 #define CONTEXT_CMD_DISABLE 0x80000000
916
917 /* GUI_STAT register constants */
918 #define ENGINE_IDLE 0
919 #define ENGINE_BUSY 1
920 #define SCISSOR_LEFT_FLAG 0x10
921 #define SCISSOR_RIGHT_FLAG 0x20
922 #define SCISSOR_TOP_FLAG 0x40
923 #define SCISSOR_BOTTOM_FLAG 0x80
924
925 /* ATI VGA Extended Regsiters */
926 #define sioATIEXT 0x1ce
927 #define bioATIEXT 0x3ce
928
929 #define ATI2E 0xae
930 #define ATI32 0xb2
931 #define ATI36 0xb6
932
933 /* VGA Graphics Controller Registers */
934 #define VGAGRA 0x3ce
935 #define GRA06 0x06
936
937 /* VGA Seququencer Registers */
938 #define VGASEQ 0x3c4
939 #define SEQ02 0x02
940 #define SEQ04 0x04
941
942 #define MACH64_MAX_X ENGINE_MAX_X
943 #define MACH64_MAX_Y ENGINE_MAX_Y
944
945 #define INC_X 0x0020
946 #define INC_Y 0x0080
947
948 #define RGB16_555 0x0000
949 #define RGB16_565 0x0040
950 #define RGB16_655 0x0080
951 #define RGB16_664 0x00c0
952
953 #define POLY_TEXT_TYPE 0x0001
954 #define IMAGE_TEXT_TYPE 0x0002
955 #define TEXT_TYPE_8_BIT 0x0004
956 #define TEXT_TYPE_16_BIT 0x0008
957 #define POLY_TEXT_TYPE_8 (POLY_TEXT_TYPE | TEXT_TYPE_8_BIT)
958 #define IMAGE_TEXT_TYPE_8 (IMAGE_TEXT_TYPE | TEXT_TYPE_8_BIT)
959 #define POLY_TEXT_TYPE_16 (POLY_TEXT_TYPE | TEXT_TYPE_16_BIT)
960 #define IMAGE_TEXT_TYPE_16 (IMAGE_TEXT_TYPE | TEXT_TYPE_16_BIT)
961
962 #define MACH64_NUM_CLOCKS 16
963 #define MACH64_NUM_FREQS 50
964
965 /* Power Management register constants (LT & LT Pro) */
966 #define PWR_MGT_ON 0x00000001
967 #define PWR_MGT_MODE_MASK 0x00000006
968 #define AUTO_PWR_UP 0x00000008
969 #define USE_F32KHZ 0x00000400
970 #define TRISTATE_MEM_EN 0x00000800
971 #define SELF_REFRESH 0x00000080
972 #define PWR_BLON 0x02000000
973 #define STANDBY_NOW 0x10000000
974 #define SUSPEND_NOW 0x20000000
975 #define PWR_MGT_STATUS_MASK 0xC0000000
976 #define PWR_MGT_STATUS_SUSPEND 0x80000000
977
978 /* PM Mode constants */
979 #define PWR_MGT_MODE_PIN 0x00000000
980 #define PWR_MGT_MODE_REG 0x00000002
981 #define PWR_MGT_MODE_TIMER 0x00000004
982 #define PWR_MGT_MODE_PCI 0x00000006
983
984 /* LCD registers (LT Pro) */
985
986 /* LCD Index register */
987 #define LCD_INDEX_MASK 0x0000003F
988 #define LCD_DISPLAY_DIS 0x00000100
989 #define LCD_SRC_SEL 0x00000200
990 #define CRTC2_DISPLAY_DIS 0x00000400
991
992 /* LCD register indices */
993 #define LCD_CONFIG_PANEL 0x00
994 #define LCD_GEN_CTRL 0x01
995 #define LCD_DSTN_CONTROL 0x02
996 #define LCD_HFB_PITCH_ADDR 0x03
997 #define LCD_HORZ_STRETCHING 0x04
998 #define LCD_VERT_STRETCHING 0x05
999 #define LCD_EXT_VERT_STRETCH 0x06
1000 #define LCD_LT_GIO 0x07
1001 #define LCD_POWER_MANAGEMENT 0x08
1002 #define LCD_ZVGPIO 0x09
1003 #define LCD_MISC_CNTL 0x14
1004
1005 /* Values in LCD_MISC_CNTL */
1006 #define BIAS_MOD_LEVEL_MASK 0x0000ff00
1007 #define BIAS_MOD_LEVEL_SHIFT 8
1008 #define BLMOD_EN 0x00010000
1009 #define BIASMOD_EN 0x00020000
1010
1011 #endif /* REGMACH64_H */
1012
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