1 /* sunhme.h: Definitions for Sparc HME/BigMac 10/100baseT ethernet driver.
2 * Also known as the "Happy Meal".
3 *
4 * Copyright (C) 1996 David S. Miller (davem@caipfs.rutgers.edu)
5 */
6
7 #ifndef _SUNHME_H
8 #define _SUNHME_H
9
10 #include <linux/config.h>
11
12 /* Happy Meal global registers. */
13 struct hmeal_gregs {
14 volatile unsigned int sw_reset; /* Software Reset */
15 volatile unsigned int cfg; /* Config Register */
16 volatile unsigned int _padding[62]; /* Unused */
17 volatile unsigned int stat; /* Status */
18 volatile unsigned int imask; /* Interrupt Mask */
19 };
20
21 /* Global reset register. */
22 #define GREG_RESET_ETX 0x01
23 #define GREG_RESET_ERX 0x02
24 #define GREG_RESET_ALL 0x03
25
26 /* Global config register. */
27 #define GREG_CFG_BURSTMSK 0x03
28 #define GREG_CFG_BURST16 0x00
29 #define GREG_CFG_BURST32 0x01
30 #define GREG_CFG_BURST64 0x02
31 #define GREG_CFG_64BIT 0x04
32 #define GREG_CFG_PARITY 0x08
33 #define GREG_CFG_RESV 0x10
34
35 /* Global status register. */
36 #define GREG_STAT_GOTFRAME 0x00000001 /* Received a frame */
37 #define GREG_STAT_RCNTEXP 0x00000002 /* Receive frame counter expired */
38 #define GREG_STAT_ACNTEXP 0x00000004 /* Align-error counter expired */
39 #define GREG_STAT_CCNTEXP 0x00000008 /* CRC-error counter expired */
40 #define GREG_STAT_LCNTEXP 0x00000010 /* Length-error counter expired */
41 #define GREG_STAT_RFIFOVF 0x00000020 /* Receive FIFO overflow */
42 #define GREG_STAT_CVCNTEXP 0x00000040 /* Code-violation counter expired */
43 #define GREG_STAT_STSTERR 0x00000080 /* Test error in XIF for SQE */
44 #define GREG_STAT_SENTFRAME 0x00000100 /* Transmitted a frame */
45 #define GREG_STAT_TFIFO_UND 0x00000200 /* Transmit FIFO underrun */
46 #define GREG_STAT_MAXPKTERR 0x00000400 /* Max-packet size error */
47 #define GREG_STAT_NCNTEXP 0x00000800 /* Normal-collision counter expired */
48 #define GREG_STAT_ECNTEXP 0x00001000 /* Excess-collision counter expired */
49 #define GREG_STAT_LCCNTEXP 0x00002000 /* Late-collision counter expired */
50 #define GREG_STAT_FCNTEXP 0x00004000 /* First-collision counter expired */
51 #define GREG_STAT_DTIMEXP 0x00008000 /* Defer-timer expired */
52 #define GREG_STAT_RXTOHOST 0x00010000 /* Moved from receive-FIFO to host memory */
53 #define GREG_STAT_NORXD 0x00020000 /* No more receive descriptors */
54 #define GREG_STAT_RXERR 0x00040000 /* Error during receive dma */
55 #define GREG_STAT_RXLATERR 0x00080000 /* Late error during receive dma */
56 #define GREG_STAT_RXPERR 0x00100000 /* Parity error during receive dma */
57 #define GREG_STAT_RXTERR 0x00200000 /* Tag error during receive dma */
58 #define GREG_STAT_EOPERR 0x00400000 /* Transmit descriptor did not have EOP set */
59 #define GREG_STAT_MIFIRQ 0x00800000 /* MIF is signaling an interrupt condition */
60 #define GREG_STAT_HOSTTOTX 0x01000000 /* Moved from host memory to transmit-FIFO */
61 #define GREG_STAT_TXALL 0x02000000 /* Transmitted all packets in the tx-fifo */
62 #define GREG_STAT_TXEACK 0x04000000 /* Error during transmit dma */
63 #define GREG_STAT_TXLERR 0x08000000 /* Late error during transmit dma */
64 #define GREG_STAT_TXPERR 0x10000000 /* Parity error during transmit dma */
65 #define GREG_STAT_TXTERR 0x20000000 /* Tag error during transmit dma */
66 #define GREG_STAT_SLVERR 0x40000000 /* PIO access got an error */
67 #define GREG_STAT_SLVPERR 0x80000000 /* PIO access got a parity error */
68
69 /* All interesting error conditions. */
70 #define GREG_STAT_ERRORS 0xfc7efefc
71
72 /* Global interrupt mask register. */
73 #define GREG_IMASK_GOTFRAME 0x00000001 /* Received a frame */
74 #define GREG_IMASK_RCNTEXP 0x00000002 /* Receive frame counter expired */
75 #define GREG_IMASK_ACNTEXP 0x00000004 /* Align-error counter expired */
76 #define GREG_IMASK_CCNTEXP 0x00000008 /* CRC-error counter expired */
77 #define GREG_IMASK_LCNTEXP 0x00000010 /* Length-error counter expired */
78 #define GREG_IMASK_RFIFOVF 0x00000020 /* Receive FIFO overflow */
79 #define GREG_IMASK_CVCNTEXP 0x00000040 /* Code-violation counter expired */
80 #define GREG_IMASK_STSTERR 0x00000080 /* Test error in XIF for SQE */
81 #define GREG_IMASK_SENTFRAME 0x00000100 /* Transmitted a frame */
82 #define GREG_IMASK_TFIFO_UND 0x00000200 /* Transmit FIFO underrun */
83 #define GREG_IMASK_MAXPKTERR 0x00000400 /* Max-packet size error */
84 #define GREG_IMASK_NCNTEXP 0x00000800 /* Normal-collision counter expired */
85 #define GREG_IMASK_ECNTEXP 0x00001000 /* Excess-collision counter expired */
86 #define GREG_IMASK_LCCNTEXP 0x00002000 /* Late-collision counter expired */
87 #define GREG_IMASK_FCNTEXP 0x00004000 /* First-collision counter expired */
88 #define GREG_IMASK_DTIMEXP 0x00008000 /* Defer-timer expired */
89 #define GREG_IMASK_RXTOHOST 0x00010000 /* Moved from receive-FIFO to host memory */
90 #define GREG_IMASK_NORXD 0x00020000 /* No more receive descriptors */
91 #define GREG_IMASK_RXERR 0x00040000 /* Error during receive dma */
92 #define GREG_IMASK_RXLATERR 0x00080000 /* Late error during receive dma */
93 #define GREG_IMASK_RXPERR 0x00100000 /* Parity error during receive dma */
94 #define GREG_IMASK_RXTERR 0x00200000 /* Tag error during receive dma */
95 #define GREG_IMASK_EOPERR 0x00400000 /* Transmit descriptor did not have EOP set */
96 #define GREG_IMASK_MIFIRQ 0x00800000 /* MIF is signaling an interrupt condition */
97 #define GREG_IMASK_HOSTTOTX 0x01000000 /* Moved from host memory to transmit-FIFO */
98 #define GREG_IMASK_TXALL 0x02000000 /* Transmitted all packets in the tx-fifo */
99 #define GREG_IMASK_TXEACK 0x04000000 /* Error during transmit dma */
100 #define GREG_IMASK_TXLERR 0x08000000 /* Late error during transmit dma */
101 #define GREG_IMASK_TXPERR 0x10000000 /* Parity error during transmit dma */
102 #define GREG_IMASK_TXTERR 0x20000000 /* Tag error during transmit dma */
103 #define GREG_IMASK_SLVERR 0x40000000 /* PIO access got an error */
104 #define GREG_IMASK_SLVPERR 0x80000000 /* PIO access got a parity error */
105
106 /* Happy Meal external transmitter registers. */
107 struct hmeal_etxregs {
108 volatile unsigned int tx_pnding; /* Transmit pending/wakeup register */
109 volatile unsigned int cfg; /* Transmit config register */
110 volatile unsigned int tx_ring; /* Transmit ring pointer */
111 volatile unsigned int tx_bbase; /* Transmit buffer base */
112 volatile unsigned int tx_bdisp; /* Transmit buffer displacement */
113 volatile unsigned int tx_fifo_wptr; /* FIFO write ptr */
114 volatile unsigned int tx_fifo_swptr; /* FIFO write ptr (shadow register) */
115 volatile unsigned int tx_fifo_rptr; /* FIFO read ptr */
116 volatile unsigned int tx_fifo_srptr; /* FIFO read ptr (shadow register) */
117 volatile unsigned int tx_fifo_pcnt; /* FIFO packet counter */
118 volatile unsigned int smachine; /* Transmitter state machine */
119 volatile unsigned int tx_rsize; /* Ring descriptor size */
120 volatile unsigned int tx_bptr; /* Transmit data buffer ptr */
121 };
122
123 /* ETX transmit pending register. */
124 #define ETX_TP_DMAWAKEUP 0x00000001 /* Restart transmit dma */
125
126 /* ETX config register. */
127 #define ETX_CFG_DMAENABLE 0x00000001 /* Enable transmit dma */
128 #define ETX_CFG_FIFOTHRESH 0x000003fe /* Transmit FIFO threshold */
129 #define ETX_CFG_IRQDAFTER 0x00000400 /* Interrupt after TX-FIFO drained */
130 #define ETX_CFG_IRQDBEFORE 0x00000000 /* Interrupt before TX-FIFO drained */
131
132 #define ETX_RSIZE_SHIFT 4
133
134 /* Happy Meal external receiver registers. */
135 struct hmeal_erxregs {
136 volatile unsigned int cfg; /* Receiver config register */
137 volatile unsigned int rx_ring; /* Receiver ring ptr */
138 volatile unsigned int rx_bptr; /* Receiver buffer ptr */
139 volatile unsigned int rx_fifo_wptr; /* FIFO write ptr */
140 volatile unsigned int rx_fifo_swptr; /* FIFO write ptr (shadow register) */
141 volatile unsigned int rx_fifo_rptr; /* FIFO read ptr */
142 volatile unsigned int rx_fifo_srptr; /* FIFO read ptr (shadow register) */
143 volatile unsigned int smachine; /* Receiver state machine */
144 };
145
146 /* ERX config register. */
147 #define ERX_CFG_DMAENABLE 0x00000001 /* Enable receive DMA */
148 #define ERX_CFG_RESV1 0x00000006 /* Unused... */
149 #define ERX_CFG_BYTEOFFSET 0x00000038 /* Receive first byte offset */
150 #define ERX_CFG_RESV2 0x000001c0 /* Unused... */
151 #define ERX_CFG_SIZE32 0x00000000 /* Receive ring size == 32 */
152 #define ERX_CFG_SIZE64 0x00000200 /* Receive ring size == 64 */
153 #define ERX_CFG_SIZE128 0x00000400 /* Receive ring size == 128 */
154 #define ERX_CFG_SIZE256 0x00000600 /* Receive ring size == 256 */
155 #define ERX_CFG_RESV3 0x0000f800 /* Unused... */
156 #define ERX_CFG_CSUMSTART 0x007f0000 /* Offset of checksum start */
157
158 /* I'd like a Big Mac, small fries, small coke, and SparcLinux please. */
159 struct hmeal_bigmacregs {
160 volatile unsigned int xif_cfg; /* XIF config register */
161 volatile unsigned int _unused[129]; /* Reserved... */
162 volatile unsigned int tx_swreset; /* Transmitter software reset */
163 volatile unsigned int tx_cfg; /* Transmitter config register */
164 volatile unsigned int ipkt_gap1; /* Inter-packet gap 1 */
165 volatile unsigned int ipkt_gap2; /* Inter-packet gap 2 */
166 volatile unsigned int attempt_limit; /* Transmit attempt limit */
167 volatile unsigned int stime; /* Transmit slot time */
168 volatile unsigned int preamble_len; /* Size of transmit preamble */
169 volatile unsigned int preamble_pattern; /* Pattern for transmit preamble */
170 volatile unsigned int tx_sframe_delim; /* Transmit delimiter */
171 volatile unsigned int jsize; /* Jam size */
172 volatile unsigned int tx_pkt_max; /* Transmit max pkt size */
173 volatile unsigned int tx_pkt_min; /* Transmit min pkt size */
174 volatile unsigned int peak_attempt; /* Count of transmit peak attempts */
175 volatile unsigned int dt_ctr; /* Transmit defer timer */
176 volatile unsigned int nc_ctr; /* Transmit normal-collision counter */
177 volatile unsigned int fc_ctr; /* Transmit first-collision counter */
178 volatile unsigned int ex_ctr; /* Transmit excess-collision counter */
179 volatile unsigned int lt_ctr; /* Transmit late-collision counter */
180 volatile unsigned int rand_seed; /* Transmit random number seed */
181 volatile unsigned int tx_smachine; /* Transmit state machine */
182 volatile unsigned int _unused2[44]; /* Reserved */
183 volatile unsigned int rx_swreset; /* Receiver software reset */
184 volatile unsigned int rx_cfg; /* Receiver config register */
185 volatile unsigned int rx_pkt_max; /* Receive max pkt size */
186 volatile unsigned int rx_pkt_min; /* Receive min pkt size */
187 volatile unsigned int mac_addr2; /* Ether address register 2 */
188 volatile unsigned int mac_addr1; /* Ether address register 1 */
189 volatile unsigned int mac_addr0; /* Ether address register 0 */
190 volatile unsigned int fr_ctr; /* Receive frame receive counter */
191 volatile unsigned int gle_ctr; /* Receive giant-length error counter */
192 volatile unsigned int unale_ctr; /* Receive unaligned error counter */
193 volatile unsigned int rcrce_ctr; /* Receive CRC error counter */
194 volatile unsigned int rx_smachine; /* Receiver state machine */
195 volatile unsigned int rx_cvalid; /* Receiver code violation */
196 volatile unsigned int _unused3; /* Reserved... */
197 volatile unsigned int htable3; /* Hash table 3 */
198 volatile unsigned int htable2; /* Hash table 2 */
199 volatile unsigned int htable1; /* Hash table 1 */
200 volatile unsigned int htable0; /* Hash table 0 */
201 volatile unsigned int afilter2; /* Address filter 2 */
202 volatile unsigned int afilter1; /* Address filter 1 */
203 volatile unsigned int afilter0; /* Address filter 0 */
204 volatile unsigned int afilter_mask; /* Address filter mask */
205
206 };
207
208 /* BigMac XIF config register. */
209 #define BIGMAC_XCFG_ODENABLE 0x00000001 /* Output driver enable */
210 #define BIGMAC_XCFG_XLBACK 0x00000002 /* Loopback-mode XIF enable */
211 #define BIGMAC_XCFG_MLBACK 0x00000004 /* Loopback-mode MII enable */
212 #define BIGMAC_XCFG_MIIDISAB 0x00000008 /* MII receive buffer disable */
213 #define BIGMAC_XCFG_SQENABLE 0x00000010 /* SQE test enable */
214 #define BIGMAC_XCFG_SQETWIN 0x000003e0 /* SQE time window */
215 #define BIGMAC_XCFG_LANCE 0x00000010 /* Lance mode enable */
216 #define BIGMAC_XCFG_LIPG0 0x000003e0 /* Lance mode IPG0 */
217
218 /* BigMac transmit config register. */
219 #define BIGMAC_TXCFG_ENABLE 0x00000001 /* Enable the transmitter */
220 #define BIGMAC_TXCFG_SMODE 0x00000020 /* Enable slow transmit mode */
221 #define BIGMAC_TXCFG_CIGN 0x00000040 /* Ignore transmit collisions */
222 #define BIGMAC_TXCFG_FCSOFF 0x00000080 /* Do not emit FCS */
223 #define BIGMAC_TXCFG_DBACKOFF 0x00000100 /* Disable backoff */
224 #define BIGMAC_TXCFG_FULLDPLX 0x00000200 /* Enable full-duplex */
225 #define BIGMAC_TXCFG_DGIVEUP 0x00000400 /* Don't give up on transmits */
226
227 /* BigMac receive config register. */
228 #define BIGMAC_RXCFG_ENABLE 0x00000001 /* Enable the receiver */
229 #define BIGMAC_RXCFG_PSTRIP 0x00000020 /* Pad byte strip enable */
230 #define BIGMAC_RXCFG_PMISC 0x00000040 /* Enable promiscous mode */
231 #define BIGMAC_RXCFG_DERR 0x00000080 /* Disable error checking */
232 #define BIGMAC_RXCFG_DCRCS 0x00000100 /* Disable CRC stripping */
233 #define BIGMAC_RXCFG_ME 0x00000200 /* Receive packets addressed to me */
234 #define BIGMAC_RXCFG_PGRP 0x00000400 /* Enable promisc group mode */
235 #define BIGMAC_RXCFG_HENABLE 0x00000800 /* Enable the hash filter */
236 #define BIGMAC_RXCFG_AENABLE 0x00001000 /* Enable the address filter */
237
238 /* These are the "Management Interface" (ie. MIF) registers of the transceiver. */
239 struct hmeal_tcvregs {
240 volatile unsigned int bb_clock; /* Bit bang clock register */
241 volatile unsigned int bb_data; /* Bit bang data register */
242 volatile unsigned int bb_oenab; /* Bit bang output enable */
243 volatile unsigned int frame; /* Frame control/data register */
244 volatile unsigned int cfg; /* MIF config register */
245 volatile unsigned int int_mask; /* MIF interrupt mask */
246 volatile unsigned int status; /* MIF status */
247 volatile unsigned int smachine; /* MIF state machine */
248 };
249
250 /* Frame commands. */
251 #define FRAME_WRITE 0x50020000
252 #define FRAME_READ 0x60020000
253
254 /* Transceiver config register */
255 #define TCV_CFG_PSELECT 0x00000001 /* Select PHY */
256 #define TCV_CFG_PENABLE 0x00000002 /* Enable MIF polling */
257 #define TCV_CFG_BENABLE 0x00000004 /* Enable the "bit banger" oh baby */
258 #define TCV_CFG_PREGADDR 0x000000f8 /* Address of poll register */
259 #define TCV_CFG_MDIO0 0x00000100 /* MDIO zero, data/attached */
260 #define TCV_CFG_MDIO1 0x00000200 /* MDIO one, data/attached */
261 #define TCV_CFG_PDADDR 0x00007c00 /* Device PHY address polling */
262
263 /* Here are some PHY addresses. */
264 #define TCV_PADDR_ETX 0 /* Internal transceiver */
265 #define TCV_PADDR_ITX 1 /* External transceiver */
266
267 /* Transceiver status register */
268 #define TCV_STAT_BASIC 0xffff0000 /* The "basic" part */
269 #define TCV_STAT_NORMAL 0x0000ffff /* The "non-basic" part */
270
271 /* Inside the Happy Meal transceiver is the physical layer, they use an
272 * implementations for National Semiconductor, part number DP83840VCE.
273 * You can retrieve the data sheets and programming docs for this beast
274 * from http://www.national.com/
275 *
276 * The DP83840 is capable of both 10 and 100Mbps ethernet, in both
277 * half and full duplex mode. It also supports auto negotiation.
278 *
279 * But.... THIS THING IS A PAIN IN THE ASS TO PROGRAM!
280 * Debugging eeprom burnt code is more fun than programming this chip!
281 */
282
283 /* First, the DP83840 register numbers. */
284 #define DP83840_BMCR 0x00 /* Basic mode control register */
285 #define DP83840_BMSR 0x01 /* Basic mode status register */
286 #define DP83840_PHYSID1 0x02 /* PHYS ID 1 */
287 #define DP83840_PHYSID2 0x03 /* PHYS ID 2 */
288 #define DP83840_ADVERTISE 0x04 /* Advertisement control reg */
289 #define DP83840_LPA 0x05 /* Link partner ability reg */
290 #define DP83840_EXPANSION 0x06 /* Expansion register */
291 #define DP83840_DCOUNTER 0x12 /* Disconnect counter */
292 #define DP83840_FCSCOUNTER 0x13 /* False carrier counter */
293 #define DP83840_NWAYTEST 0x14 /* N-way auto-neg test reg */
294 #define DP83840_RERRCOUNTER 0x15 /* Receive error counter */
295 #define DP83840_SREVISION 0x16 /* Silicon revision */
296 #define DP83840_CSCONFIG 0x17 /* CS configuration */
297 #define DP83840_LBRERROR 0x18 /* Lpback, rx, bypass error */
298 #define DP83840_PHYADDR 0x19 /* PHY address */
299 #define DP83840_RESERVED 0x1a /* Unused... */
300 #define DP83840_TPISTATUS 0x1b /* TPI status for 10mbps */
301 #define DP83840_NCONFIG 0x1c /* Network interface config */
302
303 /* Basic mode control register. */
304 #define BMCR_RESV 0x007f /* Unused... */
305 #define BMCR_CTST 0x0080 /* Collision test */
306 #define BMCR_FULLDPLX 0x0100 /* Full duplex */
307 #define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */
308 #define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */
309 #define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */
310 #define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */
311 #define BMCR_SPEED100 0x2000 /* Select 100Mbps */
312 #define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */
313 #define BMCR_RESET 0x8000 /* Reset the DP83840 */
314
315 /* Basic mode status register. */
316 #define BMSR_ERCAP 0x0001 /* Ext-reg capability */
317 #define BMSR_JCD 0x0002 /* Jabber detected */
318 #define BMSR_LSTATUS 0x0004 /* Link status */
319 #define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
320 #define BMSR_RFAULT 0x0010 /* Remote fault detected */
321 #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
322 #define BMSR_RESV 0x07c0 /* Unused... */
323 #define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */
324 #define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */
325 #define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */
326 #define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */
327 #define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */
328
329 /* Advertisement control register. */
330 #define ADVERTISE_SLCT 0x001f /* Selector bits */
331 #define ADVERTISE_CSMA 0x0001 /* Only selector supported */
332 #define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
333 #define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
334 #define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
335 #define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
336 #define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */
337 #define ADVERTISE_RESV 0x1c00 /* Unused... */
338 #define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */
339 #define ADVERTISE_LPACK 0x4000 /* Ack link partners response */
340 #define ADVERTISE_NPAGE 0x8000 /* Next page bit */
341
342 #define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
343 ADVERTISE_100HALF | ADVERTISE_100FULL)
344
345 /* Link partner ability register. */
346 #define LPA_SLCT 0x001f /* Same as advertise selector */
347 #define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */
348 #define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */
349 #define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */
350 #define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */
351 #define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */
352 #define LPA_RESV 0x1c00 /* Unused... */
353 #define LPA_RFAULT 0x2000 /* Link partner faulted */
354 #define LPA_LPACK 0x4000 /* Link partner acked us */
355 #define LPA_NPAGE 0x8000 /* Next page bit */
356
357 /* Expansion register for auto-negotiation. */
358 #define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */
359 #define EXPANSION_LCWP 0x0002 /* Got new RX page code word */
360 #define EXPANSION_ENABLENPAGE 0x0004 /* This enables npage words */
361 #define EXPANSION_NPCAPABLE 0x0008 /* Link partner supports npage */
362 #define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */
363 #define EXPANSION_RESV 0xffe0 /* Unused... */
364
365 /* N-way test register. */
366 #define NWAYTEST_RESV1 0x00ff /* Unused... */
367 #define NWAYTEST_LOOPBACK 0x0100 /* Enable loopback for N-way */
368 #define NWAYTEST_RESV2 0xfe00 /* Unused... */
369
370 /* The Carrier Sense config register. */
371 #define CSCONFIG_RESV1 0x0001 /* Unused... */
372 #define CSCONFIG_LED4 0x0002 /* Pin for full-dplx LED4 */
373 #define CSCONFIG_LED1 0x0004 /* Pin for conn-status LED1 */
374 #define CSCONFIG_RESV2 0x0008 /* Unused... */
375 #define CSCONFIG_TCVDISAB 0x0010 /* Turns off the transceiver */
376 #define CSCONFIG_DFBYPASS 0x0020 /* Bypass disconnect function */
377 #define CSCONFIG_GLFORCE 0x0040 /* Good link force for 100mbps */
378 #define CSCONFIG_CLKTRISTATE 0x0080 /* Tristate 25m clock */
379 #define CSCONFIG_RESV3 0x0700 /* Unused... */
380 #define CSCONFIG_ENCODE 0x0800 /* 1=MLT-3, 0=binary */
381 #define CSCONFIG_RENABLE 0x1000 /* Repeater mode enable */
382 #define CSCONFIG_TCDISABLE 0x2000 /* Disable timeout counter */
383 #define CSCONFIG_RESV4 0x4000 /* Unused... */
384 #define CSCONFIG_NDISABLE 0x8000 /* Disable NRZI */
385
386 /* Loopback, receive, bypass error register. */
387 #define LBRERROR_EBUFFER 0x0001 /* Show elasticity buf errors */
388 #define LBRERROR_PACKET 0x0002 /* Show packet errors */
389 #define LBRERROR_LINK 0x0004 /* Show link errors */
390 #define LBRERROR_END 0x0008 /* Show premature end errors */
391 #define LBRERROR_CODE 0x0010 /* Show code errors */
392 #define LBRERROR_RESV1 0x00e0 /* Unused... */
393 #define LBRERROR_LBACK 0x0300 /* Remote and twister loopback */
394 #define LBRERROR_10TX 0x0400 /* Transceiver loopback 10mbps */
395 #define LBRERROR_ENDEC 0x0800 /* ENDEC loopback 10mbps */
396 #define LBRERROR_ALIGN 0x1000 /* Bypass symbol alignment */
397 #define LBRERROR_SCRAMBLER 0x2000 /* Bypass (de)scrambler */
398 #define LBRERROR_ENCODER 0x4000 /* Bypass 4B5B/5B4B encoders */
399 #define LBRERROR_BEBUF 0x8000 /* Bypass elasticity buffers */
400
401 /* Physical address register. */
402 #define PHYADDR_ADDRESS 0x001f /* The address itself */
403 #define PHYADDR_DISCONNECT 0x0020 /* Disconnect status */
404 #define PHYADDR_10MBPS 0x0040 /* 1=10mbps, 0=100mbps */
405 #define PHYADDR_RESV 0xff80 /* Unused... */
406
407 /* TPI status register for 10mbps. */
408 #define TPISTATUS_RESV1 0x01ff /* Unused... */
409 #define TPISTATUS_SERIAL 0x0200 /* Enable 10mbps serial mode */
410 #define TPISTATUS_RESV2 0xfc00 /* Unused... */
411
412 /* Network interface config register. */
413 #define NCONFIG_JENABLE 0x0001 /* Jabber enable */
414 #define NCONFIG_RESV1 0x0002 /* Unused... */
415 #define NCONFIG_SQUELCH 0x0004 /* Use low squelch */
416 #define NCONFIG_UTP 0x0008 /* 1=UTP, 0=STP */
417 #define NCONFIG_HBEAT 0x0010 /* Heart-beat enable */
418 #define NCONFIG_LDISABLE 0x0020 /* Disable the link */
419 #define NCONFIG_RESV2 0xffc0 /* Unused... */
420
421 /* Happy Meal descriptor rings and such.
422 * All descriptor rings must be aligned on a 2K boundry.
423 * All receive buffers must be 64 byte aligned.
424 */
425 struct happy_meal_rxd {
426 unsigned int rx_flags;
427 unsigned int rx_addr;
428 };
429
430 #define RXFLAG_OWN 0x80000000 /* 1 = hardware, 0 = software */
431 #define RXFLAG_OVERFLOW 0x40000000 /* 1 = buffer overflow */
432 #define RXFLAG_SIZE 0x3fff0000 /* Size of the buffer */
433 #define RXFLAG_CSUM 0x0000ffff /* HW computed checksum */
434
435 struct happy_meal_txd {
436 unsigned int tx_flags;
437 unsigned int tx_addr;
438 };
439
440 #define TXFLAG_OWN 0x80000000 /* 1 = hardware, 0 = software */
441 #define TXFLAG_SOP 0x40000000 /* 1 = start of packet */
442 #define TXFLAG_EOP 0x20000000 /* 1 = end of packet */
443 #define TXFLAG_CSENABLE 0x10000000 /* 1 = enable hw-checksums */
444 #define TXFLAG_CSLOCATION 0x0ff00000 /* Where to stick the csum */
445 #define TXFLAG_CSBUFBEGIN 0x000fc000 /* Where to begin checksum */
446 #define TXFLAG_SIZE 0x00003fff /* Size of the packet */
447
448 #define TX_RING_SIZE 32 /* Must be >16 and <255, multiple of 16 */
449 #define RX_RING_SIZE 32 /* see ERX_CFG_SIZE* for possible values */
450
451 #define TX_RING_MAXSIZE 256
452 #define RX_RING_MAXSIZE 256
453
454 /* 34 byte offset for checksum computation. This works because ip_input() will clear out
455 * the skb->csum and skb->ip_summed fields and recompute the csum if IP options are
456 * present in the header. 34 == (ethernet header len) + sizeof(struct iphdr)
457 */
458 #define ERX_CFG_DEFAULT(off) (ERX_CFG_DMAENABLE|((off)<<3)|ERX_CFG_SIZE32|(0x22<<16))
459
460 #define NEXT_RX(num) (((num) + 1) & (RX_RING_SIZE - 1))
461 #define NEXT_TX(num) (((num) + 1) & (TX_RING_SIZE - 1))
462 #define PREV_RX(num) (((num) - 1) & (RX_RING_SIZE - 1))
463 #define PREV_TX(num) (((num) - 1) & (TX_RING_SIZE - 1))
464
465 #define TX_BUFFS_AVAIL(hp) \
466 (((hp)->tx_old <= (hp)->tx_new) ? \
467 (hp)->tx_old + (TX_RING_SIZE - 1) - (hp)->tx_new : \
468 (hp)->tx_old - (hp)->tx_new - 1)
469
470 #define RX_OFFSET 2
471 #define RX_BUF_ALLOC_SIZE (1546 + RX_OFFSET + 64)
472
473 #define RX_COPY_THRESHOLD 256
474
475 struct hmeal_init_block {
476 struct happy_meal_rxd happy_meal_rxd[RX_RING_MAXSIZE];
477 struct happy_meal_txd happy_meal_txd[TX_RING_MAXSIZE];
478 };
479
480 #define hblock_offset(mem, elem) \
481 ((__u32)((unsigned long)(&(((struct hmeal_init_block *)0)->mem[elem]))))
482
483 #define SUN4C_PKT_BUF_SZ 1546
484 #define SUN4C_RX_BUFF_SIZE SUN4C_PKT_BUF_SZ
485 #define SUN4C_TX_BUFF_SIZE SUN4C_PKT_BUF_SZ
486
487 struct hmeal_buffers {
488 char tx_buf[TX_RING_SIZE][SUN4C_TX_BUFF_SIZE];
489 char rx_buf[RX_RING_SIZE][SUN4C_RX_BUFF_SIZE];
490 };
491
492 #define hbuf_offset(mem, elem) \
493 ((__u32)((unsigned long)(&(((struct hmeal_buffers *)0)->mem[elem][0]))))
494
495 /* Now software state stuff. */
496 enum happy_transceiver {
497 external = 0,
498 internal = 1,
499 none = 2,
500 };
501
502 /* Timer state engine. */
503 enum happy_timer_state {
504 arbwait = 0, /* Waiting for auto negotiation to complete. */
505 lupwait = 1, /* Auto-neg complete, awaiting link-up status. */
506 ltrywait = 2, /* Forcing try of all modes, from fastest to slowest. */
507 asleep = 3, /* Time inactive. */
508 };
509
510 struct quattro;
511
512 /* Happy happy, joy joy! */
513 struct happy_meal {
514 struct hmeal_gregs *gregs; /* Happy meal global registers */
515 struct hmeal_etxregs *etxregs; /* External transmitter regs */
516 struct hmeal_erxregs *erxregs; /* External receiver regs */
517 struct hmeal_bigmacregs *bigmacregs; /* I said NO SOLARIS with my bigmac! */
518 struct hmeal_tcvregs *tcvregs; /* MIF transceiver regs */
519
520 struct hmeal_init_block *happy_block; /* RX and TX descriptors (CPU addr) */
521 __u32 hblock_dvma; /* DVMA visible address happy block */
522
523 struct sk_buff *rx_skbs[RX_RING_SIZE];
524 struct sk_buff *tx_skbs[TX_RING_SIZE];
525
526 int rx_new, tx_new, rx_old, tx_old;
527
528 /* We may use this for Ultra as well, will have to see, maybe not. */
529 struct hmeal_buffers *sun4c_buffers; /* CPU visible address. */
530 #define sun4d_buffers sun4c_buffers /* No need to make this a separate. */
531 __u32 s4c_buf_dvma; /* DVMA visible address. */
532
533 unsigned int happy_flags; /* Driver state flags */
534 enum happy_transceiver tcvr_type; /* Kind of transceiver in use */
535 unsigned int happy_bursts; /* Get your mind out of the gutter */
536 unsigned int paddr; /* PHY address for transceiver */
537 unsigned short hm_revision; /* Happy meal revision */
538 unsigned short sw_bmcr; /* SW copy of BMCR */
539 unsigned short sw_bmsr; /* SW copy of BMSR */
540 unsigned short sw_physid1; /* SW copy of PHYSID1 */
541 unsigned short sw_physid2; /* SW copy of PHYSID2 */
542 unsigned short sw_advertise; /* SW copy of ADVERTISE */
543 unsigned short sw_lpa; /* SW copy of LPA */
544 unsigned short sw_expansion; /* SW copy of EXPANSION */
545 unsigned short sw_csconfig; /* SW copy of CSCONFIG */
546 unsigned int auto_speed; /* Auto-nego link speed */
547 unsigned int forced_speed; /* Force mode link speed */
548 unsigned int poll_data; /* MIF poll data */
549 unsigned int poll_flag; /* MIF poll flag */
550 unsigned int linkcheck; /* Have we checked the link yet? */
551 unsigned int lnkup; /* Is the link up as far as we know? */
552 unsigned int lnkdown; /* Trying to force the link down? */
553 unsigned int lnkcnt; /* Counter for link-up attempts. */
554 struct timer_list happy_timer; /* To watch the link when coming up. */
555 enum happy_timer_state timer_state; /* State of the auto-neg timer. */
556 unsigned int timer_ticks; /* Number of clicks at each state. */
557
558 struct net_device_stats net_stats; /* Statistical counters */
559 struct linux_sbus_device *happy_sbus_dev; /* ;-) */
560 #ifdef CONFIG_PCI
561 struct pci_dev *happy_pci_dev;
562 #endif
563 struct device *dev; /* Backpointer */
564 struct quattro *qfe_parent; /* For Quattro cards */
565 int qfe_ent; /* Which instance on quattro */
566 struct happy_meal *next_module;
567 };
568
569 /* Here are the happy flags. */
570 #define HFLAG_POLL 0x00000001 /* We are doing MIF polling */
571 #define HFLAG_FENABLE 0x00000002 /* The MII frame is enabled */
572 #define HFLAG_LANCE 0x00000004 /* We are using lance-mode */
573 #define HFLAG_RXENABLE 0x00000008 /* Receiver is enabled */
574 #define HFLAG_AUTO 0x00000010 /* Using auto-negotiation, 0 = force */
575 #define HFLAG_FULL 0x00000020 /* Full duplex enable */
576 #define HFLAG_MACFULL 0x00000040 /* Using full duplex in the MAC */
577 #define HFLAG_POLLENABLE 0x00000080 /* Actually try MIF polling */
578 #define HFLAG_RXCV 0x00000100 /* XXX RXCV ENABLE */
579 #define HFLAG_INIT 0x00000200 /* Init called at least once */
580 #define HFLAG_LINKUP 0x00000400 /* 1 = Link is up */
581 #define HFLAG_PCI 0x00000800 /* PCI based Happy Meal */
582 #define HFLAG_QUATTRO 0x00001000 /* On QFE/Quattro card */
583
584 #define HFLAG_20_21 (HFLAG_POLLENABLE | HFLAG_FENABLE)
585 #define HFLAG_NOT_A0 (HFLAG_POLLENABLE | HFLAG_FENABLE | HFLAG_LANCE | HFLAG_RXCV)
586
587 /* Support for QFE/Quattro cards. */
588 struct quattro {
589 volatile u32 *irq_status[4];
590 struct device *happy_meals[4];
591 void (*handler)(int, void *, struct pt_regs *);
592
593 struct linux_sbus_device *quattro_sbus_dev;
594 #ifdef CONFIG_PCI
595 struct pci_dev *quattro_pci_dev;
596 #endif
597 struct quattro *next;
598
599 /* PROM ranges, if any. */
600 struct linux_prom_ranges ranges[8];
601 int nranges;
602 };
603
604 /* We use this to acquire receive skb's that we can DMA directly into. */
605 #define ALIGNED_RX_SKB_ADDR(addr) \
606 ((((unsigned long)(addr) + (64 - 1)) & ~(64 - 1)) - (unsigned long)(addr))
607 static inline struct sk_buff *happy_meal_alloc_skb(unsigned int length, int gfp_flags)
608 {
609 struct sk_buff *skb;
610
611 skb = alloc_skb(length + 64, gfp_flags);
612 if(skb) {
613 int offset = ALIGNED_RX_SKB_ADDR(skb->data);
614
615 if(offset)
616 skb_reserve(skb, offset);
617 }
618 return skb;
619 }
620
621 /* Register/DMA access stuff, used to cope with differences between
622 * PCI and SBUS happy meals.
623 */
624 extern inline u32 kva_to_hva(struct happy_meal *hp, char *addr)
625 {
626 #ifdef CONFIG_PCI
627 if(hp->happy_flags & HFLAG_PCI)
628 return (u32) virt_to_bus((volatile void *)addr);
629 else
630 #endif
631 {
632 #ifdef __sparc_v9__
633 if (((unsigned long) addr) >= MAX_DMA_ADDRESS) {
634 printk("sunhme: Bogus DMA buffer address "
635 "[%016lx]\n", ((unsigned long) addr));
636 panic("DMA address too large, tell DaveM");
637 }
638 #endif
639 return sbus_dvma_addr(addr);
640 }
641 }
642
643 extern inline unsigned int hme_read32(struct happy_meal *hp,
644 volatile unsigned int *reg)
645 {
646 #ifdef CONFIG_PCI
647 if(hp->happy_flags & HFLAG_PCI)
648 return readl((unsigned long)reg);
649 else
650 #endif
651 return *reg;
652 }
653
654 extern inline void hme_write32(struct happy_meal *hp,
655 volatile unsigned int *reg,
656 unsigned int val)
657 {
658 #ifdef CONFIG_PCI
659 if(hp->happy_flags & HFLAG_PCI)
660 writel(val, (unsigned long)reg);
661 else
662 #endif
663 *reg = val;
664 }
665
666 #ifdef CONFIG_PCI
667 #ifdef __sparc_v9__
668 extern inline void pcihme_write_rxd(struct happy_meal_rxd *rp,
669 unsigned int flags,
670 unsigned int addr)
671 {
672 __asm__ __volatile__("
673 stwa %3, [%0] %2
674 stwa %4, [%1] %2
675 " : /* no outputs */
676 : "r" (&rp->rx_addr), "r" (&rp->rx_flags),
677 "i" (ASI_PL), "r" (addr), "r" (flags));
678 }
679
680 extern inline void pcihme_write_txd(struct happy_meal_txd *tp,
681 unsigned int flags,
682 unsigned int addr)
683 {
684 __asm__ __volatile__("
685 stwa %3, [%0] %2
686 stwa %4, [%1] %2
687 " : /* no outputs */
688 : "r" (&tp->tx_addr), "r" (&tp->tx_flags),
689 "i" (ASI_PL), "r" (addr), "r" (flags));
690 }
691 #else
692
693 extern inline void pcihme_write_rxd(struct happy_meal_rxd *rp,
694 unsigned int flags,
695 unsigned int addr)
696 {
697 rp->rx_addr = flip_dword(addr);
698 rp->rx_flags = flip_dword(flags);
699 }
700
701 extern inline void pcihme_write_txd(struct happy_meal_txd *tp,
702 unsigned int flags,
703 unsigned int addr)
704 {
705 tp->tx_addr = flip_dword(addr);
706 tp->tx_flags = flip_dword(flags);
707 }
708
709 #endif /* def __sparc_v9__ */
710 #endif /* def CONFIG_PCI */
711
712 #endif /* !(_SUNHME_H) */
713
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