1 /* $Id: sunhme.h,v 1.31 2000/11/12 10:23:30 davem Exp $
2 * sunhme.h: Definitions for Sparc HME/BigMac 10/100baseT ethernet driver.
3 * Also known as the "Happy Meal".
4 *
5 * Copyright (C) 1996, 1999 David S. Miller (davem@redhat.com)
6 */
7
8 #ifndef _SUNHME_H
9 #define _SUNHME_H
10
11 #include <linux/config.h>
12 #include <linux/pci.h>
13
14 /* Happy Meal global registers. */
15 #define GREG_SWRESET 0x000UL /* Software Reset */
16 #define GREG_CFG 0x004UL /* Config Register */
17 #define GREG_STAT 0x108UL /* Status */
18 #define GREG_IMASK 0x10cUL /* Interrupt Mask */
19 #define GREG_REG_SIZE 0x110UL
20
21 /* Global reset register. */
22 #define GREG_RESET_ETX 0x01
23 #define GREG_RESET_ERX 0x02
24 #define GREG_RESET_ALL 0x03
25
26 /* Global config register. */
27 #define GREG_CFG_BURSTMSK 0x03
28 #define GREG_CFG_BURST16 0x00
29 #define GREG_CFG_BURST32 0x01
30 #define GREG_CFG_BURST64 0x02
31 #define GREG_CFG_64BIT 0x04
32 #define GREG_CFG_PARITY 0x08
33 #define GREG_CFG_RESV 0x10
34
35 /* Global status register. */
36 #define GREG_STAT_GOTFRAME 0x00000001 /* Received a frame */
37 #define GREG_STAT_RCNTEXP 0x00000002 /* Receive frame counter expired */
38 #define GREG_STAT_ACNTEXP 0x00000004 /* Align-error counter expired */
39 #define GREG_STAT_CCNTEXP 0x00000008 /* CRC-error counter expired */
40 #define GREG_STAT_LCNTEXP 0x00000010 /* Length-error counter expired */
41 #define GREG_STAT_RFIFOVF 0x00000020 /* Receive FIFO overflow */
42 #define GREG_STAT_CVCNTEXP 0x00000040 /* Code-violation counter expired */
43 #define GREG_STAT_STSTERR 0x00000080 /* Test error in XIF for SQE */
44 #define GREG_STAT_SENTFRAME 0x00000100 /* Transmitted a frame */
45 #define GREG_STAT_TFIFO_UND 0x00000200 /* Transmit FIFO underrun */
46 #define GREG_STAT_MAXPKTERR 0x00000400 /* Max-packet size error */
47 #define GREG_STAT_NCNTEXP 0x00000800 /* Normal-collision counter expired */
48 #define GREG_STAT_ECNTEXP 0x00001000 /* Excess-collision counter expired */
49 #define GREG_STAT_LCCNTEXP 0x00002000 /* Late-collision counter expired */
50 #define GREG_STAT_FCNTEXP 0x00004000 /* First-collision counter expired */
51 #define GREG_STAT_DTIMEXP 0x00008000 /* Defer-timer expired */
52 #define GREG_STAT_RXTOHOST 0x00010000 /* Moved from receive-FIFO to host memory */
53 #define GREG_STAT_NORXD 0x00020000 /* No more receive descriptors */
54 #define GREG_STAT_RXERR 0x00040000 /* Error during receive dma */
55 #define GREG_STAT_RXLATERR 0x00080000 /* Late error during receive dma */
56 #define GREG_STAT_RXPERR 0x00100000 /* Parity error during receive dma */
57 #define GREG_STAT_RXTERR 0x00200000 /* Tag error during receive dma */
58 #define GREG_STAT_EOPERR 0x00400000 /* Transmit descriptor did not have EOP set */
59 #define GREG_STAT_MIFIRQ 0x00800000 /* MIF is signaling an interrupt condition */
60 #define GREG_STAT_HOSTTOTX 0x01000000 /* Moved from host memory to transmit-FIFO */
61 #define GREG_STAT_TXALL 0x02000000 /* Transmitted all packets in the tx-fifo */
62 #define GREG_STAT_TXEACK 0x04000000 /* Error during transmit dma */
63 #define GREG_STAT_TXLERR 0x08000000 /* Late error during transmit dma */
64 #define GREG_STAT_TXPERR 0x10000000 /* Parity error during transmit dma */
65 #define GREG_STAT_TXTERR 0x20000000 /* Tag error during transmit dma */
66 #define GREG_STAT_SLVERR 0x40000000 /* PIO access got an error */
67 #define GREG_STAT_SLVPERR 0x80000000 /* PIO access got a parity error */
68
69 /* All interesting error conditions. */
70 #define GREG_STAT_ERRORS 0xfc7efefc
71
72 /* Global interrupt mask register. */
73 #define GREG_IMASK_GOTFRAME 0x00000001 /* Received a frame */
74 #define GREG_IMASK_RCNTEXP 0x00000002 /* Receive frame counter expired */
75 #define GREG_IMASK_ACNTEXP 0x00000004 /* Align-error counter expired */
76 #define GREG_IMASK_CCNTEXP 0x00000008 /* CRC-error counter expired */
77 #define GREG_IMASK_LCNTEXP 0x00000010 /* Length-error counter expired */
78 #define GREG_IMASK_RFIFOVF 0x00000020 /* Receive FIFO overflow */
79 #define GREG_IMASK_CVCNTEXP 0x00000040 /* Code-violation counter expired */
80 #define GREG_IMASK_STSTERR 0x00000080 /* Test error in XIF for SQE */
81 #define GREG_IMASK_SENTFRAME 0x00000100 /* Transmitted a frame */
82 #define GREG_IMASK_TFIFO_UND 0x00000200 /* Transmit FIFO underrun */
83 #define GREG_IMASK_MAXPKTERR 0x00000400 /* Max-packet size error */
84 #define GREG_IMASK_NCNTEXP 0x00000800 /* Normal-collision counter expired */
85 #define GREG_IMASK_ECNTEXP 0x00001000 /* Excess-collision counter expired */
86 #define GREG_IMASK_LCCNTEXP 0x00002000 /* Late-collision counter expired */
87 #define GREG_IMASK_FCNTEXP 0x00004000 /* First-collision counter expired */
88 #define GREG_IMASK_DTIMEXP 0x00008000 /* Defer-timer expired */
89 #define GREG_IMASK_RXTOHOST 0x00010000 /* Moved from receive-FIFO to host memory */
90 #define GREG_IMASK_NORXD 0x00020000 /* No more receive descriptors */
91 #define GREG_IMASK_RXERR 0x00040000 /* Error during receive dma */
92 #define GREG_IMASK_RXLATERR 0x00080000 /* Late error during receive dma */
93 #define GREG_IMASK_RXPERR 0x00100000 /* Parity error during receive dma */
94 #define GREG_IMASK_RXTERR 0x00200000 /* Tag error during receive dma */
95 #define GREG_IMASK_EOPERR 0x00400000 /* Transmit descriptor did not have EOP set */
96 #define GREG_IMASK_MIFIRQ 0x00800000 /* MIF is signaling an interrupt condition */
97 #define GREG_IMASK_HOSTTOTX 0x01000000 /* Moved from host memory to transmit-FIFO */
98 #define GREG_IMASK_TXALL 0x02000000 /* Transmitted all packets in the tx-fifo */
99 #define GREG_IMASK_TXEACK 0x04000000 /* Error during transmit dma */
100 #define GREG_IMASK_TXLERR 0x08000000 /* Late error during transmit dma */
101 #define GREG_IMASK_TXPERR 0x10000000 /* Parity error during transmit dma */
102 #define GREG_IMASK_TXTERR 0x20000000 /* Tag error during transmit dma */
103 #define GREG_IMASK_SLVERR 0x40000000 /* PIO access got an error */
104 #define GREG_IMASK_SLVPERR 0x80000000 /* PIO access got a parity error */
105
106 /* Happy Meal external transmitter registers. */
107 #define ETX_PENDING 0x00UL /* Transmit pending/wakeup register */
108 #define ETX_CFG 0x04UL /* Transmit config register */
109 #define ETX_RING 0x08UL /* Transmit ring pointer */
110 #define ETX_BBASE 0x0cUL /* Transmit buffer base */
111 #define ETX_BDISP 0x10UL /* Transmit buffer displacement */
112 #define ETX_FIFOWPTR 0x14UL /* FIFO write ptr */
113 #define ETX_FIFOSWPTR 0x18UL /* FIFO write ptr (shadow register) */
114 #define ETX_FIFORPTR 0x1cUL /* FIFO read ptr */
115 #define ETX_FIFOSRPTR 0x20UL /* FIFO read ptr (shadow register) */
116 #define ETX_FIFOPCNT 0x24UL /* FIFO packet counter */
117 #define ETX_SMACHINE 0x28UL /* Transmitter state machine */
118 #define ETX_RSIZE 0x2cUL /* Ring descriptor size */
119 #define ETX_BPTR 0x30UL /* Transmit data buffer ptr */
120 #define ETX_REG_SIZE 0x34UL
121
122 /* ETX transmit pending register. */
123 #define ETX_TP_DMAWAKEUP 0x00000001 /* Restart transmit dma */
124
125 /* ETX config register. */
126 #define ETX_CFG_DMAENABLE 0x00000001 /* Enable transmit dma */
127 #define ETX_CFG_FIFOTHRESH 0x000003fe /* Transmit FIFO threshold */
128 #define ETX_CFG_IRQDAFTER 0x00000400 /* Interrupt after TX-FIFO drained */
129 #define ETX_CFG_IRQDBEFORE 0x00000000 /* Interrupt before TX-FIFO drained */
130
131 #define ETX_RSIZE_SHIFT 4
132
133 /* Happy Meal external receiver registers. */
134 #define ERX_CFG 0x00UL /* Receiver config register */
135 #define ERX_RING 0x04UL /* Receiver ring ptr */
136 #define ERX_BPTR 0x08UL /* Receiver buffer ptr */
137 #define ERX_FIFOWPTR 0x0cUL /* FIFO write ptr */
138 #define ERX_FIFOSWPTR 0x10UL /* FIFO write ptr (shadow register) */
139 #define ERX_FIFORPTR 0x14UL /* FIFO read ptr */
140 #define ERX_FIFOSRPTR 0x18UL /* FIFO read ptr (shadow register) */
141 #define ERX_SMACHINE 0x1cUL /* Receiver state machine */
142 #define ERX_REG_SIZE 0x20UL
143
144 /* ERX config register. */
145 #define ERX_CFG_DMAENABLE 0x00000001 /* Enable receive DMA */
146 #define ERX_CFG_RESV1 0x00000006 /* Unused... */
147 #define ERX_CFG_BYTEOFFSET 0x00000038 /* Receive first byte offset */
148 #define ERX_CFG_RESV2 0x000001c0 /* Unused... */
149 #define ERX_CFG_SIZE32 0x00000000 /* Receive ring size == 32 */
150 #define ERX_CFG_SIZE64 0x00000200 /* Receive ring size == 64 */
151 #define ERX_CFG_SIZE128 0x00000400 /* Receive ring size == 128 */
152 #define ERX_CFG_SIZE256 0x00000600 /* Receive ring size == 256 */
153 #define ERX_CFG_RESV3 0x0000f800 /* Unused... */
154 #define ERX_CFG_CSUMSTART 0x007f0000 /* Offset of checksum start */
155
156 /* I'd like a Big Mac, small fries, small coke, and SparcLinux please. */
157 #define BMAC_XIFCFG 0x0000UL /* XIF config register */
158 /* 0x4-->0x204, reserved */
159 #define BMAC_TXSWRESET 0x208UL /* Transmitter software reset */
160 #define BMAC_TXCFG 0x20cUL /* Transmitter config register */
161 #define BMAC_IGAP1 0x210UL /* Inter-packet gap 1 */
162 #define BMAC_IGAP2 0x214UL /* Inter-packet gap 2 */
163 #define BMAC_ALIMIT 0x218UL /* Transmit attempt limit */
164 #define BMAC_STIME 0x21cUL /* Transmit slot time */
165 #define BMAC_PLEN 0x220UL /* Size of transmit preamble */
166 #define BMAC_PPAT 0x224UL /* Pattern for transmit preamble */
167 #define BMAC_TXSDELIM 0x228UL /* Transmit delimiter */
168 #define BMAC_JSIZE 0x22cUL /* Jam size */
169 #define BMAC_TXMAX 0x230UL /* Transmit max pkt size */
170 #define BMAC_TXMIN 0x234UL /* Transmit min pkt size */
171 #define BMAC_PATTEMPT 0x238UL /* Count of transmit peak attempts */
172 #define BMAC_DTCTR 0x23cUL /* Transmit defer timer */
173 #define BMAC_NCCTR 0x240UL /* Transmit normal-collision counter */
174 #define BMAC_FCCTR 0x244UL /* Transmit first-collision counter */
175 #define BMAC_EXCTR 0x248UL /* Transmit excess-collision counter */
176 #define BMAC_LTCTR 0x24cUL /* Transmit late-collision counter */
177 #define BMAC_RSEED 0x250UL /* Transmit random number seed */
178 #define BMAC_TXSMACHINE 0x254UL /* Transmit state machine */
179 /* 0x258-->0x304, reserved */
180 #define BMAC_RXSWRESET 0x308UL /* Receiver software reset */
181 #define BMAC_RXCFG 0x30cUL /* Receiver config register */
182 #define BMAC_RXMAX 0x310UL /* Receive max pkt size */
183 #define BMAC_RXMIN 0x314UL /* Receive min pkt size */
184 #define BMAC_MACADDR2 0x318UL /* Ether address register 2 */
185 #define BMAC_MACADDR1 0x31cUL /* Ether address register 1 */
186 #define BMAC_MACADDR0 0x320UL /* Ether address register 0 */
187 #define BMAC_FRCTR 0x324UL /* Receive frame receive counter */
188 #define BMAC_GLECTR 0x328UL /* Receive giant-length error counter */
189 #define BMAC_UNALECTR 0x32cUL /* Receive unaligned error counter */
190 #define BMAC_RCRCECTR 0x330UL /* Receive CRC error counter */
191 #define BMAC_RXSMACHINE 0x334UL /* Receiver state machine */
192 #define BMAC_RXCVALID 0x338UL /* Receiver code violation */
193 /* 0x33c, reserved */
194 #define BMAC_HTABLE3 0x340UL /* Hash table 3 */
195 #define BMAC_HTABLE2 0x344UL /* Hash table 2 */
196 #define BMAC_HTABLE1 0x348UL /* Hash table 1 */
197 #define BMAC_HTABLE0 0x34cUL /* Hash table 0 */
198 #define BMAC_AFILTER2 0x350UL /* Address filter 2 */
199 #define BMAC_AFILTER1 0x354UL /* Address filter 1 */
200 #define BMAC_AFILTER0 0x358UL /* Address filter 0 */
201 #define BMAC_AFMASK 0x35cUL /* Address filter mask */
202 #define BMAC_REG_SIZE 0x360UL
203
204 /* BigMac XIF config register. */
205 #define BIGMAC_XCFG_ODENABLE 0x00000001 /* Output driver enable */
206 #define BIGMAC_XCFG_XLBACK 0x00000002 /* Loopback-mode XIF enable */
207 #define BIGMAC_XCFG_MLBACK 0x00000004 /* Loopback-mode MII enable */
208 #define BIGMAC_XCFG_MIIDISAB 0x00000008 /* MII receive buffer disable */
209 #define BIGMAC_XCFG_SQENABLE 0x00000010 /* SQE test enable */
210 #define BIGMAC_XCFG_SQETWIN 0x000003e0 /* SQE time window */
211 #define BIGMAC_XCFG_LANCE 0x00000010 /* Lance mode enable */
212 #define BIGMAC_XCFG_LIPG0 0x000003e0 /* Lance mode IPG0 */
213
214 /* BigMac transmit config register. */
215 #define BIGMAC_TXCFG_ENABLE 0x00000001 /* Enable the transmitter */
216 #define BIGMAC_TXCFG_SMODE 0x00000020 /* Enable slow transmit mode */
217 #define BIGMAC_TXCFG_CIGN 0x00000040 /* Ignore transmit collisions */
218 #define BIGMAC_TXCFG_FCSOFF 0x00000080 /* Do not emit FCS */
219 #define BIGMAC_TXCFG_DBACKOFF 0x00000100 /* Disable backoff */
220 #define BIGMAC_TXCFG_FULLDPLX 0x00000200 /* Enable full-duplex */
221 #define BIGMAC_TXCFG_DGIVEUP 0x00000400 /* Don't give up on transmits */
222
223 /* BigMac receive config register. */
224 #define BIGMAC_RXCFG_ENABLE 0x00000001 /* Enable the receiver */
225 #define BIGMAC_RXCFG_PSTRIP 0x00000020 /* Pad byte strip enable */
226 #define BIGMAC_RXCFG_PMISC 0x00000040 /* Enable promiscous mode */
227 #define BIGMAC_RXCFG_DERR 0x00000080 /* Disable error checking */
228 #define BIGMAC_RXCFG_DCRCS 0x00000100 /* Disable CRC stripping */
229 #define BIGMAC_RXCFG_ME 0x00000200 /* Receive packets addressed to me */
230 #define BIGMAC_RXCFG_PGRP 0x00000400 /* Enable promisc group mode */
231 #define BIGMAC_RXCFG_HENABLE 0x00000800 /* Enable the hash filter */
232 #define BIGMAC_RXCFG_AENABLE 0x00001000 /* Enable the address filter */
233
234 /* These are the "Management Interface" (ie. MIF) registers of the transceiver. */
235 #define TCVR_BBCLOCK 0x00UL /* Bit bang clock register */
236 #define TCVR_BBDATA 0x04UL /* Bit bang data register */
237 #define TCVR_BBOENAB 0x08UL /* Bit bang output enable */
238 #define TCVR_FRAME 0x0cUL /* Frame control/data register */
239 #define TCVR_CFG 0x10UL /* MIF config register */
240 #define TCVR_IMASK 0x14UL /* MIF interrupt mask */
241 #define TCVR_STATUS 0x18UL /* MIF status */
242 #define TCVR_SMACHINE 0x1cUL /* MIF state machine */
243 #define TCVR_REG_SIZE 0x20UL
244
245 /* Frame commands. */
246 #define FRAME_WRITE 0x50020000
247 #define FRAME_READ 0x60020000
248
249 /* Transceiver config register */
250 #define TCV_CFG_PSELECT 0x00000001 /* Select PHY */
251 #define TCV_CFG_PENABLE 0x00000002 /* Enable MIF polling */
252 #define TCV_CFG_BENABLE 0x00000004 /* Enable the "bit banger" oh baby */
253 #define TCV_CFG_PREGADDR 0x000000f8 /* Address of poll register */
254 #define TCV_CFG_MDIO0 0x00000100 /* MDIO zero, data/attached */
255 #define TCV_CFG_MDIO1 0x00000200 /* MDIO one, data/attached */
256 #define TCV_CFG_PDADDR 0x00007c00 /* Device PHY address polling */
257
258 /* Here are some PHY addresses. */
259 #define TCV_PADDR_ETX 0 /* Internal transceiver */
260 #define TCV_PADDR_ITX 1 /* External transceiver */
261
262 /* Transceiver status register */
263 #define TCV_STAT_BASIC 0xffff0000 /* The "basic" part */
264 #define TCV_STAT_NORMAL 0x0000ffff /* The "non-basic" part */
265
266 /* Inside the Happy Meal transceiver is the physical layer, they use an
267 * implementations for National Semiconductor, part number DP83840VCE.
268 * You can retrieve the data sheets and programming docs for this beast
269 * from http://www.national.com/
270 *
271 * The DP83840 is capable of both 10 and 100Mbps ethernet, in both
272 * half and full duplex mode. It also supports auto negotiation.
273 *
274 * But.... THIS THING IS A PAIN IN THE ASS TO PROGRAM!
275 * Debugging eeprom burnt code is more fun than programming this chip!
276 */
277
278 /* First, the DP83840 register numbers. */
279 #define DP83840_BMCR 0x00 /* Basic mode control register */
280 #define DP83840_BMSR 0x01 /* Basic mode status register */
281 #define DP83840_PHYSID1 0x02 /* PHYS ID 1 */
282 #define DP83840_PHYSID2 0x03 /* PHYS ID 2 */
283 #define DP83840_ADVERTISE 0x04 /* Advertisement control reg */
284 #define DP83840_LPA 0x05 /* Link partner ability reg */
285 #define DP83840_EXPANSION 0x06 /* Expansion register */
286 #define DP83840_DCOUNTER 0x12 /* Disconnect counter */
287 #define DP83840_FCSCOUNTER 0x13 /* False carrier counter */
288 #define DP83840_NWAYTEST 0x14 /* N-way auto-neg test reg */
289 #define DP83840_RERRCOUNTER 0x15 /* Receive error counter */
290 #define DP83840_SREVISION 0x16 /* Silicon revision */
291 #define DP83840_CSCONFIG 0x17 /* CS configuration */
292 #define DP83840_LBRERROR 0x18 /* Lpback, rx, bypass error */
293 #define DP83840_PHYADDR 0x19 /* PHY address */
294 #define DP83840_RESERVED 0x1a /* Unused... */
295 #define DP83840_TPISTATUS 0x1b /* TPI status for 10mbps */
296 #define DP83840_NCONFIG 0x1c /* Network interface config */
297
298 /* Basic mode control register. */
299 #define BMCR_RESV 0x007f /* Unused... */
300 #define BMCR_CTST 0x0080 /* Collision test */
301 #define BMCR_FULLDPLX 0x0100 /* Full duplex */
302 #define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */
303 #define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */
304 #define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */
305 #define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */
306 #define BMCR_SPEED100 0x2000 /* Select 100Mbps */
307 #define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */
308 #define BMCR_RESET 0x8000 /* Reset the DP83840 */
309
310 /* Basic mode status register. */
311 #define BMSR_ERCAP 0x0001 /* Ext-reg capability */
312 #define BMSR_JCD 0x0002 /* Jabber detected */
313 #define BMSR_LSTATUS 0x0004 /* Link status */
314 #define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
315 #define BMSR_RFAULT 0x0010 /* Remote fault detected */
316 #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
317 #define BMSR_RESV 0x07c0 /* Unused... */
318 #define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */
319 #define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */
320 #define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */
321 #define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */
322 #define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */
323
324 /* Advertisement control register. */
325 #define ADVERTISE_SLCT 0x001f /* Selector bits */
326 #define ADVERTISE_CSMA 0x0001 /* Only selector supported */
327 #define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
328 #define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
329 #define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
330 #define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
331 #define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */
332 #define ADVERTISE_RESV 0x1c00 /* Unused... */
333 #define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */
334 #define ADVERTISE_LPACK 0x4000 /* Ack link partners response */
335 #define ADVERTISE_NPAGE 0x8000 /* Next page bit */
336
337 #define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
338 ADVERTISE_100HALF | ADVERTISE_100FULL)
339
340 /* Link partner ability register. */
341 #define LPA_SLCT 0x001f /* Same as advertise selector */
342 #define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */
343 #define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */
344 #define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */
345 #define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */
346 #define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */
347 #define LPA_RESV 0x1c00 /* Unused... */
348 #define LPA_RFAULT 0x2000 /* Link partner faulted */
349 #define LPA_LPACK 0x4000 /* Link partner acked us */
350 #define LPA_NPAGE 0x8000 /* Next page bit */
351
352 /* Expansion register for auto-negotiation. */
353 #define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */
354 #define EXPANSION_LCWP 0x0002 /* Got new RX page code word */
355 #define EXPANSION_ENABLENPAGE 0x0004 /* This enables npage words */
356 #define EXPANSION_NPCAPABLE 0x0008 /* Link partner supports npage */
357 #define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */
358 #define EXPANSION_RESV 0xffe0 /* Unused... */
359
360 /* N-way test register. */
361 #define NWAYTEST_RESV1 0x00ff /* Unused... */
362 #define NWAYTEST_LOOPBACK 0x0100 /* Enable loopback for N-way */
363 #define NWAYTEST_RESV2 0xfe00 /* Unused... */
364
365 /* The Carrier Sense config register. */
366 #define CSCONFIG_RESV1 0x0001 /* Unused... */
367 #define CSCONFIG_LED4 0x0002 /* Pin for full-dplx LED4 */
368 #define CSCONFIG_LED1 0x0004 /* Pin for conn-status LED1 */
369 #define CSCONFIG_RESV2 0x0008 /* Unused... */
370 #define CSCONFIG_TCVDISAB 0x0010 /* Turns off the transceiver */
371 #define CSCONFIG_DFBYPASS 0x0020 /* Bypass disconnect function */
372 #define CSCONFIG_GLFORCE 0x0040 /* Good link force for 100mbps */
373 #define CSCONFIG_CLKTRISTATE 0x0080 /* Tristate 25m clock */
374 #define CSCONFIG_RESV3 0x0700 /* Unused... */
375 #define CSCONFIG_ENCODE 0x0800 /* 1=MLT-3, 0=binary */
376 #define CSCONFIG_RENABLE 0x1000 /* Repeater mode enable */
377 #define CSCONFIG_TCDISABLE 0x2000 /* Disable timeout counter */
378 #define CSCONFIG_RESV4 0x4000 /* Unused... */
379 #define CSCONFIG_NDISABLE 0x8000 /* Disable NRZI */
380
381 /* Loopback, receive, bypass error register. */
382 #define LBRERROR_EBUFFER 0x0001 /* Show elasticity buf errors */
383 #define LBRERROR_PACKET 0x0002 /* Show packet errors */
384 #define LBRERROR_LINK 0x0004 /* Show link errors */
385 #define LBRERROR_END 0x0008 /* Show premature end errors */
386 #define LBRERROR_CODE 0x0010 /* Show code errors */
387 #define LBRERROR_RESV1 0x00e0 /* Unused... */
388 #define LBRERROR_LBACK 0x0300 /* Remote and twister loopback */
389 #define LBRERROR_10TX 0x0400 /* Transceiver loopback 10mbps */
390 #define LBRERROR_ENDEC 0x0800 /* ENDEC loopback 10mbps */
391 #define LBRERROR_ALIGN 0x1000 /* Bypass symbol alignment */
392 #define LBRERROR_SCRAMBLER 0x2000 /* Bypass (de)scrambler */
393 #define LBRERROR_ENCODER 0x4000 /* Bypass 4B5B/5B4B encoders */
394 #define LBRERROR_BEBUF 0x8000 /* Bypass elasticity buffers */
395
396 /* Physical address register. */
397 #define PHYADDR_ADDRESS 0x001f /* The address itself */
398 #define PHYADDR_DISCONNECT 0x0020 /* Disconnect status */
399 #define PHYADDR_10MBPS 0x0040 /* 1=10mbps, 0=100mbps */
400 #define PHYADDR_RESV 0xff80 /* Unused... */
401
402 /* TPI status register for 10mbps. */
403 #define TPISTATUS_RESV1 0x01ff /* Unused... */
404 #define TPISTATUS_SERIAL 0x0200 /* Enable 10mbps serial mode */
405 #define TPISTATUS_RESV2 0xfc00 /* Unused... */
406
407 /* Network interface config register. */
408 #define NCONFIG_JENABLE 0x0001 /* Jabber enable */
409 #define NCONFIG_RESV1 0x0002 /* Unused... */
410 #define NCONFIG_SQUELCH 0x0004 /* Use low squelch */
411 #define NCONFIG_UTP 0x0008 /* 1=UTP, 0=STP */
412 #define NCONFIG_HBEAT 0x0010 /* Heart-beat enable */
413 #define NCONFIG_LDISABLE 0x0020 /* Disable the link */
414 #define NCONFIG_RESV2 0xffc0 /* Unused... */
415
416 /* Happy Meal descriptor rings and such.
417 * All descriptor rings must be aligned on a 2K boundry.
418 * All receive buffers must be 64 byte aligned.
419 * Always write the address first before setting the ownership
420 * bits to avoid races with the hardware scanning the ring.
421 */
422 struct happy_meal_rxd {
423 u32 rx_flags;
424 u32 rx_addr;
425 };
426
427 #define RXFLAG_OWN 0x80000000 /* 1 = hardware, 0 = software */
428 #define RXFLAG_OVERFLOW 0x40000000 /* 1 = buffer overflow */
429 #define RXFLAG_SIZE 0x3fff0000 /* Size of the buffer */
430 #define RXFLAG_CSUM 0x0000ffff /* HW computed checksum */
431
432 struct happy_meal_txd {
433 u32 tx_flags;
434 u32 tx_addr;
435 };
436
437 #define TXFLAG_OWN 0x80000000 /* 1 = hardware, 0 = software */
438 #define TXFLAG_SOP 0x40000000 /* 1 = start of packet */
439 #define TXFLAG_EOP 0x20000000 /* 1 = end of packet */
440 #define TXFLAG_CSENABLE 0x10000000 /* 1 = enable hw-checksums */
441 #define TXFLAG_CSLOCATION 0x0ff00000 /* Where to stick the csum */
442 #define TXFLAG_CSBUFBEGIN 0x000fc000 /* Where to begin checksum */
443 #define TXFLAG_SIZE 0x00003fff /* Size of the packet */
444
445 #define TX_RING_SIZE 32 /* Must be >16 and <255, multiple of 16 */
446 #define RX_RING_SIZE 32 /* see ERX_CFG_SIZE* for possible values */
447
448 #define TX_RING_MAXSIZE 256
449 #define RX_RING_MAXSIZE 256
450
451 /* 34 byte offset for checksum computation. This works because ip_input() will clear out
452 * the skb->csum and skb->ip_summed fields and recompute the csum if IP options are
453 * present in the header. 34 == (ethernet header len) + sizeof(struct iphdr)
454 */
455 #define ERX_CFG_DEFAULT(off) (ERX_CFG_DMAENABLE|((off)<<3)|ERX_CFG_SIZE32|(0x22<<16))
456
457 #define NEXT_RX(num) (((num) + 1) & (RX_RING_SIZE - 1))
458 #define NEXT_TX(num) (((num) + 1) & (TX_RING_SIZE - 1))
459 #define PREV_RX(num) (((num) - 1) & (RX_RING_SIZE - 1))
460 #define PREV_TX(num) (((num) - 1) & (TX_RING_SIZE - 1))
461
462 #define TX_BUFFS_AVAIL(hp) \
463 (((hp)->tx_old <= (hp)->tx_new) ? \
464 (hp)->tx_old + (TX_RING_SIZE - 1) - (hp)->tx_new : \
465 (hp)->tx_old - (hp)->tx_new - 1)
466
467 #define RX_OFFSET 2
468 #define RX_BUF_ALLOC_SIZE (1546 + RX_OFFSET + 64)
469
470 #define RX_COPY_THRESHOLD 256
471
472 struct hmeal_init_block {
473 struct happy_meal_rxd happy_meal_rxd[RX_RING_MAXSIZE];
474 struct happy_meal_txd happy_meal_txd[TX_RING_MAXSIZE];
475 };
476
477 #define hblock_offset(mem, elem) \
478 ((__u32)((unsigned long)(&(((struct hmeal_init_block *)0)->mem[elem]))))
479
480 /* Now software state stuff. */
481 enum happy_transceiver {
482 external = 0,
483 internal = 1,
484 none = 2,
485 };
486
487 /* Timer state engine. */
488 enum happy_timer_state {
489 arbwait = 0, /* Waiting for auto negotiation to complete. */
490 lupwait = 1, /* Auto-neg complete, awaiting link-up status. */
491 ltrywait = 2, /* Forcing try of all modes, from fastest to slowest. */
492 asleep = 3, /* Time inactive. */
493 };
494
495 struct quattro;
496
497 /* Happy happy, joy joy! */
498 struct happy_meal {
499 unsigned long gregs; /* Happy meal global registers */
500 struct hmeal_init_block *happy_block; /* RX and TX descriptors (CPU addr) */
501
502 #if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
503 u32 (*read_desc32)(u32 *);
504 void (*write_txd)(struct happy_meal_txd *, u32, u32);
505 void (*write_rxd)(struct happy_meal_rxd *, u32, u32);
506 u32 (*dma_map)(void *, void *, long, int);
507 void (*dma_unmap)(void *, u32, long, int);
508 void (*dma_sync)(void *, u32, long, int);
509 #endif
510
511 /* This is either a sbus_dev or a pci_dev. */
512 void *happy_dev;
513
514 spinlock_t happy_lock;
515
516 struct sk_buff *rx_skbs[RX_RING_SIZE];
517 struct sk_buff *tx_skbs[TX_RING_SIZE];
518
519 int rx_new, tx_new, rx_old, tx_old;
520
521 struct net_device_stats net_stats; /* Statistical counters */
522
523 #if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
524 u32 (*read32)(unsigned long);
525 void (*write32)(unsigned long, u32);
526 #endif
527
528 unsigned long etxregs; /* External transmitter regs */
529 unsigned long erxregs; /* External receiver regs */
530 unsigned long bigmacregs; /* BIGMAC core regs */
531 unsigned long tcvregs; /* MIF transceiver regs */
532
533 __u32 hblock_dvma; /* DVMA visible address happy block */
534 unsigned int happy_flags; /* Driver state flags */
535 enum happy_transceiver tcvr_type; /* Kind of transceiver in use */
536 unsigned int happy_bursts; /* Get your mind out of the gutter */
537 unsigned int paddr; /* PHY address for transceiver */
538 unsigned short hm_revision; /* Happy meal revision */
539 unsigned short sw_bmcr; /* SW copy of BMCR */
540 unsigned short sw_bmsr; /* SW copy of BMSR */
541 unsigned short sw_physid1; /* SW copy of PHYSID1 */
542 unsigned short sw_physid2; /* SW copy of PHYSID2 */
543 unsigned short sw_advertise; /* SW copy of ADVERTISE */
544 unsigned short sw_lpa; /* SW copy of LPA */
545 unsigned short sw_expansion; /* SW copy of EXPANSION */
546 unsigned short sw_csconfig; /* SW copy of CSCONFIG */
547 unsigned int auto_speed; /* Auto-nego link speed */
548 unsigned int forced_speed; /* Force mode link speed */
549 unsigned int poll_data; /* MIF poll data */
550 unsigned int poll_flag; /* MIF poll flag */
551 unsigned int linkcheck; /* Have we checked the link yet? */
552 unsigned int lnkup; /* Is the link up as far as we know? */
553 unsigned int lnkdown; /* Trying to force the link down? */
554 unsigned int lnkcnt; /* Counter for link-up attempts. */
555 struct timer_list happy_timer; /* To watch the link when coming up. */
556 enum happy_timer_state timer_state; /* State of the auto-neg timer. */
557 unsigned int timer_ticks; /* Number of clicks at each state. */
558
559 struct net_device *dev; /* Backpointer */
560 struct quattro *qfe_parent; /* For Quattro cards */
561 int qfe_ent; /* Which instance on quattro */
562 struct happy_meal *next_module;
563 };
564
565 /* Here are the happy flags. */
566 #define HFLAG_POLL 0x00000001 /* We are doing MIF polling */
567 #define HFLAG_FENABLE 0x00000002 /* The MII frame is enabled */
568 #define HFLAG_LANCE 0x00000004 /* We are using lance-mode */
569 #define HFLAG_RXENABLE 0x00000008 /* Receiver is enabled */
570 #define HFLAG_AUTO 0x00000010 /* Using auto-negotiation, 0 = force */
571 #define HFLAG_FULL 0x00000020 /* Full duplex enable */
572 #define HFLAG_MACFULL 0x00000040 /* Using full duplex in the MAC */
573 #define HFLAG_POLLENABLE 0x00000080 /* Actually try MIF polling */
574 #define HFLAG_RXCV 0x00000100 /* XXX RXCV ENABLE */
575 #define HFLAG_INIT 0x00000200 /* Init called at least once */
576 #define HFLAG_LINKUP 0x00000400 /* 1 = Link is up */
577 #define HFLAG_PCI 0x00000800 /* PCI based Happy Meal */
578 #define HFLAG_QUATTRO 0x00001000 /* On QFE/Quattro card */
579
580 #define HFLAG_20_21 (HFLAG_POLLENABLE | HFLAG_FENABLE)
581 #define HFLAG_NOT_A0 (HFLAG_POLLENABLE | HFLAG_FENABLE | HFLAG_LANCE | HFLAG_RXCV)
582
583 /* Support for QFE/Quattro cards. */
584 struct quattro {
585 struct net_device *happy_meals[4];
586
587 /* This is either a sbus_dev or a pci_dev. */
588 void *quattro_dev;
589
590 struct quattro *next;
591
592 /* PROM ranges, if any. */
593 #ifdef CONFIG_SBUS
594 struct linux_prom_ranges ranges[8];
595 #endif
596 int nranges;
597 };
598
599 /* We use this to acquire receive skb's that we can DMA directly into. */
600 #define ALIGNED_RX_SKB_ADDR(addr) \
601 ((((unsigned long)(addr) + (64UL - 1UL)) & ~(64UL - 1UL)) - (unsigned long)(addr))
602 #define happy_meal_alloc_skb(__length, __gfp_flags) \
603 ({ struct sk_buff *__skb; \
604 __skb = alloc_skb((__length) + 64, (__gfp_flags)); \
605 if(__skb) { \
606 int __offset = (int) ALIGNED_RX_SKB_ADDR(__skb->data); \
607 if(__offset) \
608 skb_reserve(__skb, __offset); \
609 } \
610 __skb; \
611 })
612
613 #endif /* !(_SUNHME_H) */
614
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