1 /* $Id: sunhme.c,v 1.122 2001/08/13 14:40:07 davem Exp $
2 * sunhme.c: Sparc HME/BigMac 10/100baseT half/full duplex auto switching,
3 * auto carrier detecting ethernet driver. Also known as the
4 * "Happy Meal Ethernet" found on SunSwift SBUS cards.
5 *
6 * Copyright (C) 1996, 1998, 1999 David S. Miller (davem@redhat.com)
7 *
8 * Changes :
9 * 2000/11/11 Willy Tarreau <willy AT meta-x.org>
10 * - port to non-sparc architectures. Tested only on x86 and
11 * only currently works with QFE PCI cards.
12 * - ability to specify the MAC address at module load time by passing this
13 * argument : macaddr=0x00,0x10,0x20,0x30,0x40,0x50
14 */
15
16 static char version[] =
17 "sunhme.c:v1.99 12/Sep/99 David S. Miller (davem@redhat.com)\n";
18
19 #include <linux/module.h>
20
21 #include <linux/config.h>
22 #include <linux/kernel.h>
23 #include <linux/sched.h>
24 #include <linux/types.h>
25 #include <linux/fcntl.h>
26 #include <linux/interrupt.h>
27 #include <linux/ptrace.h>
28 #include <linux/ioport.h>
29 #include <linux/in.h>
30 #include <linux/slab.h>
31 #include <linux/string.h>
32 #include <linux/delay.h>
33 #include <linux/init.h>
34 #include <linux/ethtool.h>
35 #include <linux/mii.h>
36 #include <asm/system.h>
37 #include <asm/bitops.h>
38 #include <asm/io.h>
39 #include <asm/dma.h>
40 #include <linux/errno.h>
41 #include <asm/byteorder.h>
42
43 #ifdef __sparc__
44 #include <asm/idprom.h>
45 #include <asm/sbus.h>
46 #include <asm/openprom.h>
47 #include <asm/oplib.h>
48 #include <asm/auxio.h>
49 #ifndef __sparc_v9__
50 #include <asm/io-unit.h>
51 #endif
52 #endif
53 #include <asm/uaccess.h>
54
55 #include <asm/pgtable.h>
56 #include <asm/irq.h>
57
58 #include <linux/netdevice.h>
59 #include <linux/etherdevice.h>
60 #include <linux/skbuff.h>
61
62 #ifdef CONFIG_PCI
63 #include <linux/pci.h>
64 #ifdef __sparc__
65 #include <asm/pbm.h>
66 #endif
67 #endif
68
69 #include "sunhme.h"
70
71
72 static int macaddr[6];
73
74 /* accept MAC address of the form macaddr=0x08,0x00,0x20,0x30,0x40,0x50 */
75 MODULE_PARM(macaddr, "6i");
76 MODULE_PARM_DESC(macaddr, "Happy Meal MAC address to set");
77
78 static struct happy_meal *root_happy_dev;
79
80 #ifdef CONFIG_SBUS
81 static struct quattro *qfe_sbus_list;
82 #endif
83
84 #ifdef CONFIG_PCI
85 static struct quattro *qfe_pci_list;
86 #endif
87
88 #undef HMEDEBUG
89 #undef SXDEBUG
90 #undef RXDEBUG
91 #undef TXDEBUG
92 #undef TXLOGGING
93
94 #ifdef TXLOGGING
95 struct hme_tx_logent {
96 unsigned int tstamp;
97 int tx_new, tx_old;
98 unsigned int action;
99 #define TXLOG_ACTION_IRQ 0x01
100 #define TXLOG_ACTION_TXMIT 0x02
101 #define TXLOG_ACTION_TBUSY 0x04
102 #define TXLOG_ACTION_NBUFS 0x08
103 unsigned int status;
104 };
105 #define TX_LOG_LEN 128
106 static struct hme_tx_logent tx_log[TX_LOG_LEN];
107 static int txlog_cur_entry;
108 static __inline__ void tx_add_log(struct happy_meal *hp, unsigned int a, unsigned int s)
109 {
110 struct hme_tx_logent *tlp;
111 unsigned long flags;
112
113 save_and_cli(flags);
114 tlp = &tx_log[txlog_cur_entry];
115 tlp->tstamp = (unsigned int)jiffies;
116 tlp->tx_new = hp->tx_new;
117 tlp->tx_old = hp->tx_old;
118 tlp->action = a;
119 tlp->status = s;
120 txlog_cur_entry = (txlog_cur_entry + 1) & (TX_LOG_LEN - 1);
121 restore_flags(flags);
122 }
123 static __inline__ void tx_dump_log(void)
124 {
125 int i, this;
126
127 this = txlog_cur_entry;
128 for (i = 0; i < TX_LOG_LEN; i++) {
129 printk("TXLOG[%d]: j[%08x] tx[N(%d)O(%d)] action[%08x] stat[%08x]\n", i,
130 tx_log[this].tstamp,
131 tx_log[this].tx_new, tx_log[this].tx_old,
132 tx_log[this].action, tx_log[this].status);
133 this = (this + 1) & (TX_LOG_LEN - 1);
134 }
135 }
136 static __inline__ void tx_dump_ring(struct happy_meal *hp)
137 {
138 struct hmeal_init_block *hb = hp->happy_block;
139 struct happy_meal_txd *tp = &hb->happy_meal_txd[0];
140 int i;
141
142 for (i = 0; i < TX_RING_SIZE; i+=4) {
143 printk("TXD[%d..%d]: [%08x:%08x] [%08x:%08x] [%08x:%08x] [%08x:%08x]\n",
144 i, i + 4,
145 le32_to_cpu(tp[i].tx_flags), le32_to_cpu(tp[i].tx_addr),
146 le32_to_cpu(tp[i + 1].tx_flags), le32_to_cpu(tp[i + 1].tx_addr),
147 le32_to_cpu(tp[i + 2].tx_flags), le32_to_cpu(tp[i + 2].tx_addr),
148 le32_to_cpu(tp[i + 3].tx_flags), le32_to_cpu(tp[i + 3].tx_addr));
149 }
150 }
151 #else
152 #define tx_add_log(hp, a, s) do { } while(0)
153 #define tx_dump_log() do { } while(0)
154 #define tx_dump_ring(hp) do { } while(0)
155 #endif
156
157 #ifdef HMEDEBUG
158 #define HMD(x) printk x
159 #else
160 #define HMD(x)
161 #endif
162
163 /* #define AUTO_SWITCH_DEBUG */
164
165 #ifdef AUTO_SWITCH_DEBUG
166 #define ASD(x) printk x
167 #else
168 #define ASD(x)
169 #endif
170
171 #define DEFAULT_IPG0 16 /* For lance-mode only */
172 #define DEFAULT_IPG1 8 /* For all modes */
173 #define DEFAULT_IPG2 4 /* For all modes */
174 #define DEFAULT_JAMSIZE 4 /* Toe jam */
175
176 #ifdef CONFIG_PCI
177 /* This happy_pci_ids is declared __initdata because it is only used
178 as an advisory to depmod. If this is ported to the new PCI interface
179 where it could be referenced at any time due to hot plugging,
180 it should be changed to __devinitdata. */
181
182 struct pci_device_id happymeal_pci_ids[] __initdata = {
183 {
184 vendor: PCI_VENDOR_ID_SUN,
185 device: PCI_DEVICE_ID_SUN_HAPPYMEAL,
186 subvendor: PCI_ANY_ID,
187 subdevice: PCI_ANY_ID,
188 },
189 { } /* Terminating entry */
190 };
191
192 MODULE_DEVICE_TABLE(pci, happymeal_pci_ids);
193 #endif
194
195 /* NOTE: In the descriptor writes one _must_ write the address
196 * member _first_. The card must not be allowed to see
197 * the updated descriptor flags until the address is
198 * correct. I've added a write memory barrier between
199 * the two stores so that I can sleep well at night... -DaveM
200 */
201
202 #if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
203 static void sbus_hme_write32(unsigned long reg, u32 val)
204 {
205 sbus_writel(val, reg);
206 }
207
208 static u32 sbus_hme_read32(unsigned long reg)
209 {
210 return sbus_readl(reg);
211 }
212
213 static void sbus_hme_write_rxd(struct happy_meal_rxd *rxd, u32 flags, u32 addr)
214 {
215 rxd->rx_addr = addr;
216 wmb();
217 rxd->rx_flags = flags;
218 }
219
220 static void sbus_hme_write_txd(struct happy_meal_txd *txd, u32 flags, u32 addr)
221 {
222 txd->tx_addr = addr;
223 wmb();
224 txd->tx_flags = flags;
225 }
226
227 static u32 sbus_hme_read_desc32(u32 *p)
228 {
229 return *p;
230 }
231
232 static void pci_hme_write32(unsigned long reg, u32 val)
233 {
234 writel(val, reg);
235 }
236
237 static u32 pci_hme_read32(unsigned long reg)
238 {
239 return readl(reg);
240 }
241
242 static void pci_hme_write_rxd(struct happy_meal_rxd *rxd, u32 flags, u32 addr)
243 {
244 rxd->rx_addr = cpu_to_le32(addr);
245 wmb();
246 rxd->rx_flags = cpu_to_le32(flags);
247 }
248
249 static void pci_hme_write_txd(struct happy_meal_txd *txd, u32 flags, u32 addr)
250 {
251 txd->tx_addr = cpu_to_le32(addr);
252 wmb();
253 txd->tx_flags = cpu_to_le32(flags);
254 }
255
256 static u32 pci_hme_read_desc32(u32 *p)
257 {
258 return cpu_to_le32p(p);
259 }
260
261 #define hme_write32(__hp, __reg, __val) \
262 ((__hp)->write32((__reg), (__val)))
263 #define hme_read32(__hp, __reg) \
264 ((__hp)->read32(__reg))
265 #define hme_write_rxd(__hp, __rxd, __flags, __addr) \
266 ((__hp)->write_rxd((__rxd), (__flags), (__addr)))
267 #define hme_write_txd(__hp, __txd, __flags, __addr) \
268 ((__hp)->write_txd((__txd), (__flags), (__addr)))
269 #define hme_read_desc32(__hp, __p) \
270 ((__hp)->read_desc32(__p))
271 #define hme_dma_map(__hp, __ptr, __size, __dir) \
272 ((__hp)->dma_map((__hp)->happy_dev, (__ptr), (__size), (__dir)))
273 #define hme_dma_unmap(__hp, __addr, __size, __dir) \
274 ((__hp)->dma_unmap((__hp)->happy_dev, (__addr), (__size), (__dir)))
275 #define hme_dma_sync(__hp, __addr, __size, __dir) \
276 ((__hp)->dma_sync((__hp)->happy_dev, (__addr), (__size), (__dir)))
277 #else
278 #ifdef CONFIG_SBUS
279 /* SBUS only compilation */
280 #define hme_write32(__hp, __reg, __val) \
281 sbus_writel((__val), (__reg))
282 #define hme_read32(__hp, __reg) \
283 sbus_readl(__reg)
284 #define hme_write_rxd(__hp, __rxd, __flags, __addr) \
285 do { (__rxd)->rx_addr = (__addr); \
286 wmb(); \
287 (__rxd)->rx_flags = (__flags); \
288 } while(0)
289 #define hme_write_txd(__hp, __txd, __flags, __addr) \
290 do { (__txd)->tx_addr = (__addr); \
291 wmb(); \
292 (__txd)->tx_flags = (__flags); \
293 } while(0)
294 #define hme_read_desc32(__hp, __p) (*(__p))
295 #define hme_dma_map(__hp, __ptr, __size, __dir) \
296 sbus_map_single((__hp)->happy_dev, (__ptr), (__size), (__dir))
297 #define hme_dma_unmap(__hp, __addr, __size, __dir) \
298 sbus_unmap_single((__hp)->happy_dev, (__addr), (__size), (__dir))
299 #define hme_dma_sync(__hp, __addr, __size, __dir) \
300 sbus_dma_sync_single((__hp)->happy_dev, (__addr), (__size), (__dir))
301 #else
302 /* PCI only compilation */
303 #define hme_write32(__hp, __reg, __val) \
304 writel((__val), (__reg))
305 #define hme_read32(__hp, __reg) \
306 readl(__reg)
307 #define hme_write_rxd(__hp, __rxd, __flags, __addr) \
308 do { (__rxd)->rx_addr = cpu_to_le32(__addr); \
309 wmb(); \
310 (__rxd)->rx_flags = cpu_to_le32(__flags); \
311 } while(0)
312 #define hme_write_txd(__hp, __txd, __flags, __addr) \
313 do { (__txd)->tx_addr = cpu_to_le32(__addr); \
314 wmb(); \
315 (__txd)->tx_flags = cpu_to_le32(__flags); \
316 } while(0)
317 #define hme_read_desc32(__hp, __p) cpu_to_le32p(__p)
318 #define hme_dma_map(__hp, __ptr, __size, __dir) \
319 pci_map_single((__hp)->happy_dev, (__ptr), (__size), (__dir))
320 #define hme_dma_unmap(__hp, __addr, __size, __dir) \
321 pci_unmap_single((__hp)->happy_dev, (__addr), (__size), (__dir))
322 #define hme_dma_sync(__hp, __addr, __size, __dir) \
323 pci_dma_sync_single((__hp)->happy_dev, (__addr), (__size), (__dir))
324 #endif
325 #endif
326
327
328 #ifdef SBUS_DMA_BIDIRECTIONAL
329 # define DMA_BIDIRECTIONAL SBUS_DMA_BIDIRECTIONAL
330 #else
331 # define DMA_BIDIRECTIONAL 0
332 #endif
333
334 #ifdef SBUS_DMA_FROMDEVICE
335 # define DMA_FROMDEVICE SBUS_DMA_FROMDEVICE
336 #else
337 # define DMA_TODEVICE 1
338 #endif
339
340 #ifdef SBUS_DMA_TODEVICE
341 # define DMA_TODEVICE SBUS_DMA_TODEVICE
342 #else
343 # define DMA_FROMDEVICE 2
344 #endif
345
346
347 /* Oh yes, the MIF BitBang is mighty fun to program. BitBucket is more like it. */
348 static void BB_PUT_BIT(struct happy_meal *hp, unsigned long tregs, int bit)
349 {
350 hme_write32(hp, tregs + TCVR_BBDATA, bit);
351 hme_write32(hp, tregs + TCVR_BBCLOCK, 0);
352 hme_write32(hp, tregs + TCVR_BBCLOCK, 1);
353 }
354
355 #if 0
356 static u32 BB_GET_BIT(struct happy_meal *hp, unsigned long tregs, int internal)
357 {
358 u32 ret;
359
360 hme_write32(hp, tregs + TCVR_BBCLOCK, 0);
361 hme_write32(hp, tregs + TCVR_BBCLOCK, 1);
362 ret = hme_read32(hp, tregs + TCVR_CFG);
363 if (internal)
364 ret &= TCV_CFG_MDIO0;
365 else
366 ret &= TCV_CFG_MDIO1;
367
368 return ret;
369 }
370 #endif
371
372 static u32 BB_GET_BIT2(struct happy_meal *hp, unsigned long tregs, int internal)
373 {
374 u32 retval;
375
376 hme_write32(hp, tregs + TCVR_BBCLOCK, 0);
377 udelay(1);
378 retval = hme_read32(hp, tregs + TCVR_CFG);
379 if (internal)
380 retval &= TCV_CFG_MDIO0;
381 else
382 retval &= TCV_CFG_MDIO1;
383 hme_write32(hp, tregs + TCVR_BBCLOCK, 1);
384
385 return retval;
386 }
387
388 #define TCVR_FAILURE 0x80000000 /* Impossible MIF read value */
389
390 static int happy_meal_bb_read(struct happy_meal *hp,
391 unsigned long tregs, int reg)
392 {
393 u32 tmp;
394 int retval = 0;
395 int i;
396
397 ASD(("happy_meal_bb_read: reg=%d ", reg));
398
399 /* Enable the MIF BitBang outputs. */
400 hme_write32(hp, tregs + TCVR_BBOENAB, 1);
401
402 /* Force BitBang into the idle state. */
403 for (i = 0; i < 32; i++)
404 BB_PUT_BIT(hp, tregs, 1);
405
406 /* Give it the read sequence. */
407 BB_PUT_BIT(hp, tregs, 0);
408 BB_PUT_BIT(hp, tregs, 1);
409 BB_PUT_BIT(hp, tregs, 1);
410 BB_PUT_BIT(hp, tregs, 0);
411
412 /* Give it the PHY address. */
413 tmp = hp->paddr & 0xff;
414 for (i = 4; i >= 0; i--)
415 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
416
417 /* Tell it what register we want to read. */
418 tmp = (reg & 0xff);
419 for (i = 4; i >= 0; i--)
420 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
421
422 /* Close down the MIF BitBang outputs. */
423 hme_write32(hp, tregs + TCVR_BBOENAB, 0);
424
425 /* Now read in the value. */
426 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
427 for (i = 15; i >= 0; i--)
428 retval |= BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
429 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
430 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
431 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
432 ASD(("value=%x\n", retval));
433 return retval;
434 }
435
436 static void happy_meal_bb_write(struct happy_meal *hp,
437 unsigned long tregs, int reg,
438 unsigned short value)
439 {
440 u32 tmp;
441 int i;
442
443 ASD(("happy_meal_bb_write: reg=%d value=%x\n", reg, value));
444
445 /* Enable the MIF BitBang outputs. */
446 hme_write32(hp, tregs + TCVR_BBOENAB, 1);
447
448 /* Force BitBang into the idle state. */
449 for (i = 0; i < 32; i++)
450 BB_PUT_BIT(hp, tregs, 1);
451
452 /* Give it write sequence. */
453 BB_PUT_BIT(hp, tregs, 0);
454 BB_PUT_BIT(hp, tregs, 1);
455 BB_PUT_BIT(hp, tregs, 0);
456 BB_PUT_BIT(hp, tregs, 1);
457
458 /* Give it the PHY address. */
459 tmp = (hp->paddr & 0xff);
460 for (i = 4; i >= 0; i--)
461 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
462
463 /* Tell it what register we will be writing. */
464 tmp = (reg & 0xff);
465 for (i = 4; i >= 0; i--)
466 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
467
468 /* Tell it to become ready for the bits. */
469 BB_PUT_BIT(hp, tregs, 1);
470 BB_PUT_BIT(hp, tregs, 0);
471
472 for (i = 15; i >= 0; i--)
473 BB_PUT_BIT(hp, tregs, ((value >> i) & 1));
474
475 /* Close down the MIF BitBang outputs. */
476 hme_write32(hp, tregs + TCVR_BBOENAB, 0);
477 }
478
479 #define TCVR_READ_TRIES 16
480
481 static int happy_meal_tcvr_read(struct happy_meal *hp,
482 unsigned long tregs, int reg)
483 {
484 int tries = TCVR_READ_TRIES;
485 int retval;
486
487 ASD(("happy_meal_tcvr_read: reg=0x%02x ", reg));
488 if (hp->tcvr_type == none) {
489 ASD(("no transceiver, value=TCVR_FAILURE\n"));
490 return TCVR_FAILURE;
491 }
492
493 if (!(hp->happy_flags & HFLAG_FENABLE)) {
494 ASD(("doing bit bang\n"));
495 return happy_meal_bb_read(hp, tregs, reg);
496 }
497
498 hme_write32(hp, tregs + TCVR_FRAME,
499 (FRAME_READ | (hp->paddr << 23) | ((reg & 0xff) << 18)));
500 while (!(hme_read32(hp, tregs + TCVR_FRAME) & 0x10000) && --tries)
501 udelay(20);
502 if (!tries) {
503 printk(KERN_ERR "happy meal: Aieee, transceiver MIF read bolixed\n");
504 return TCVR_FAILURE;
505 }
506 retval = hme_read32(hp, tregs + TCVR_FRAME) & 0xffff;
507 ASD(("value=%04x\n", retval));
508 return retval;
509 }
510
511 #define TCVR_WRITE_TRIES 16
512
513 static void happy_meal_tcvr_write(struct happy_meal *hp,
514 unsigned long tregs, int reg,
515 unsigned short value)
516 {
517 int tries = TCVR_WRITE_TRIES;
518
519 ASD(("happy_meal_tcvr_write: reg=0x%02x value=%04x\n", reg, value));
520
521 /* Welcome to Sun Microsystems, can I take your order please? */
522 if (!hp->happy_flags & HFLAG_FENABLE)
523 return happy_meal_bb_write(hp, tregs, reg, value);
524
525 /* Would you like fries with that? */
526 hme_write32(hp, tregs + TCVR_FRAME,
527 (FRAME_WRITE | (hp->paddr << 23) |
528 ((reg & 0xff) << 18) | (value & 0xffff)));
529 while (!(hme_read32(hp, tregs + TCVR_FRAME) & 0x10000) && --tries)
530 udelay(20);
531
532 /* Anything else? */
533 if (!tries)
534 printk(KERN_ERR "happy meal: Aieee, transceiver MIF write bolixed\n");
535
536 /* Fifty-two cents is your change, have a nice day. */
537 }
538
539 /* Auto negotiation. The scheme is very simple. We have a timer routine
540 * that keeps watching the auto negotiation process as it progresses.
541 * The DP83840 is first told to start doing it's thing, we set up the time
542 * and place the timer state machine in it's initial state.
543 *
544 * Here the timer peeks at the DP83840 status registers at each click to see
545 * if the auto negotiation has completed, we assume here that the DP83840 PHY
546 * will time out at some point and just tell us what (didn't) happen. For
547 * complete coverage we only allow so many of the ticks at this level to run,
548 * when this has expired we print a warning message and try another strategy.
549 * This "other" strategy is to force the interface into various speed/duplex
550 * configurations and we stop when we see a link-up condition before the
551 * maximum number of "peek" ticks have occurred.
552 *
553 * Once a valid link status has been detected we configure the BigMAC and
554 * the rest of the Happy Meal to speak the most efficient protocol we could
555 * get a clean link for. The priority for link configurations, highest first
556 * is:
557 * 100 Base-T Full Duplex
558 * 100 Base-T Half Duplex
559 * 10 Base-T Full Duplex
560 * 10 Base-T Half Duplex
561 *
562 * We start a new timer now, after a successful auto negotiation status has
563 * been detected. This timer just waits for the link-up bit to get set in
564 * the BMCR of the DP83840. When this occurs we print a kernel log message
565 * describing the link type in use and the fact that it is up.
566 *
567 * If a fatal error of some sort is signalled and detected in the interrupt
568 * service routine, and the chip is reset, or the link is ifconfig'd down
569 * and then back up, this entire process repeats itself all over again.
570 */
571 static int try_next_permutation(struct happy_meal *hp, unsigned long tregs)
572 {
573 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
574
575 /* Downgrade from full to half duplex. Only possible
576 * via ethtool.
577 */
578 if (hp->sw_bmcr & BMCR_FULLDPLX) {
579 hp->sw_bmcr &= ~(BMCR_FULLDPLX);
580 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
581 return 0;
582 }
583
584 /* Downgrade from 100 to 10. */
585 if (hp->sw_bmcr & BMCR_SPEED100) {
586 hp->sw_bmcr &= ~(BMCR_SPEED100);
587 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
588 return 0;
589 }
590
591 /* We've tried everything. */
592 return -1;
593 }
594
595 static void display_link_mode(struct happy_meal *hp, unsigned long tregs)
596 {
597 printk(KERN_INFO "%s: Link is up using ", hp->dev->name);
598 if (hp->tcvr_type == external)
599 printk("external ");
600 else
601 printk("internal ");
602 printk("transceiver at ");
603 hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, MII_LPA);
604 if (hp->sw_lpa & (LPA_100HALF | LPA_100FULL)) {
605 if (hp->sw_lpa & LPA_100FULL)
606 printk("100Mb/s, Full Duplex.\n");
607 else
608 printk("100Mb/s, Half Duplex.\n");
609 } else {
610 if (hp->sw_lpa & LPA_10FULL)
611 printk("10Mb/s, Full Duplex.\n");
612 else
613 printk("10Mb/s, Half Duplex.\n");
614 }
615 }
616
617 static void display_forced_link_mode(struct happy_meal *hp, unsigned long tregs)
618 {
619 printk(KERN_INFO "%s: Link has been forced up using ", hp->dev->name);
620 if (hp->tcvr_type == external)
621 printk("external ");
622 else
623 printk("internal ");
624 printk("transceiver at ");
625 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
626 if (hp->sw_bmcr & BMCR_SPEED100)
627 printk("100Mb/s, ");
628 else
629 printk("10Mb/s, ");
630 if (hp->sw_bmcr & BMCR_FULLDPLX)
631 printk("Full Duplex.\n");
632 else
633 printk("Half Duplex.\n");
634 }
635
636 static int set_happy_link_modes(struct happy_meal *hp, unsigned long tregs)
637 {
638 int full;
639
640 /* All we care about is making sure the bigmac tx_cfg has a
641 * proper duplex setting.
642 */
643 if (hp->timer_state == arbwait) {
644 hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, MII_LPA);
645 if (!(hp->sw_lpa & (LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL)))
646 goto no_response;
647 if (hp->sw_lpa & LPA_100FULL)
648 full = 1;
649 else if (hp->sw_lpa & LPA_100HALF)
650 full = 0;
651 else if (hp->sw_lpa & LPA_10FULL)
652 full = 1;
653 else
654 full = 0;
655 } else {
656 /* Forcing a link mode. */
657 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
658 if (hp->sw_bmcr & BMCR_FULLDPLX)
659 full = 1;
660 else
661 full = 0;
662 }
663
664 /* Before changing other bits in the tx_cfg register, and in
665 * general any of other the TX config registers too, you
666 * must:
667 * 1) Clear Enable
668 * 2) Poll with reads until that bit reads back as zero
669 * 3) Make TX configuration changes
670 * 4) Set Enable once more
671 */
672 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
673 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) &
674 ~(BIGMAC_TXCFG_ENABLE));
675 while (hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) & BIGMAC_TXCFG_ENABLE)
676 barrier();
677 if (full) {
678 hp->happy_flags |= HFLAG_FULL;
679 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
680 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) |
681 BIGMAC_TXCFG_FULLDPLX);
682 } else {
683 hp->happy_flags &= ~(HFLAG_FULL);
684 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
685 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) &
686 ~(BIGMAC_TXCFG_FULLDPLX));
687 }
688 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
689 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) |
690 BIGMAC_TXCFG_ENABLE);
691 return 0;
692 no_response:
693 return 1;
694 }
695
696 static int happy_meal_init(struct happy_meal *hp, int from_irq);
697
698 static int is_lucent_phy(struct happy_meal *hp)
699 {
700 unsigned long tregs = hp->tcvregs;
701 unsigned short mr2, mr3;
702 int ret = 0;
703
704 mr2 = happy_meal_tcvr_read(hp, tregs, 2);
705 mr3 = happy_meal_tcvr_read(hp, tregs, 3);
706 if ((mr2 & 0xffff) == 0x0180 &&
707 ((mr3 & 0xffff) >> 10) == 0x1d) {
708 #if 0
709 printk("HMEDEBUG: Lucent PHY detected.\n");
710 #endif
711 ret = 1;
712 }
713
714 return ret;
715 }
716
717 static void happy_meal_timer(unsigned long data)
718 {
719 struct happy_meal *hp = (struct happy_meal *) data;
720 unsigned long tregs = hp->tcvregs;
721 int restart_timer = 0;
722
723 hp->timer_ticks++;
724 switch(hp->timer_state) {
725 case arbwait:
726 /* Only allow for 5 ticks, thats 10 seconds and much too
727 * long to wait for arbitration to complete.
728 */
729 if (hp->timer_ticks >= 10) {
730 /* Enter force mode. */
731 do_force_mode:
732 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
733 printk(KERN_NOTICE "%s: Auto-Negotiation unsuccessful, trying force link mode\n",
734 hp->dev->name);
735 hp->sw_bmcr = BMCR_SPEED100;
736 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
737
738 if (!is_lucent_phy(hp)) {
739 /* OK, seems we need do disable the transceiver for the first
740 * tick to make sure we get an accurate link state at the
741 * second tick.
742 */
743 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs, DP83840_CSCONFIG);
744 hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB);
745 happy_meal_tcvr_write(hp, tregs, DP83840_CSCONFIG, hp->sw_csconfig);
746 }
747 hp->timer_state = ltrywait;
748 hp->timer_ticks = 0;
749 restart_timer = 1;
750 } else {
751 /* Anything interesting happen? */
752 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
753 if (hp->sw_bmsr & BMSR_ANEGCOMPLETE) {
754 int ret;
755
756 /* Just what we've been waiting for... */
757 ret = set_happy_link_modes(hp, tregs);
758 if (ret) {
759 /* Ooops, something bad happened, go to force
760 * mode.
761 *
762 * XXX Broken hubs which don't support 802.3u
763 * XXX auto-negotiation make this happen as well.
764 */
765 goto do_force_mode;
766 }
767
768 /* Success, at least so far, advance our state engine. */
769 hp->timer_state = lupwait;
770 restart_timer = 1;
771 } else {
772 restart_timer = 1;
773 }
774 }
775 break;
776
777 case lupwait:
778 /* Auto negotiation was successful and we are awaiting a
779 * link up status. I have decided to let this timer run
780 * forever until some sort of error is signalled, reporting
781 * a message to the user at 10 second intervals.
782 */
783 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
784 if (hp->sw_bmsr & BMSR_LSTATUS) {
785 /* Wheee, it's up, display the link mode in use and put
786 * the timer to sleep.
787 */
788 display_link_mode(hp, tregs);
789 hp->timer_state = asleep;
790 restart_timer = 0;
791 } else {
792 if (hp->timer_ticks >= 10) {
793 printk(KERN_NOTICE "%s: Auto negotiation successful, link still "
794 "not completely up.\n", hp->dev->name);
795 hp->timer_ticks = 0;
796 restart_timer = 1;
797 } else {
798 restart_timer = 1;
799 }
800 }
801 break;
802
803 case ltrywait:
804 /* Making the timeout here too long can make it take
805 * annoyingly long to attempt all of the link mode
806 * permutations, but then again this is essentially
807 * error recovery code for the most part.
808 */
809 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
810 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs, DP83840_CSCONFIG);
811 if (hp->timer_ticks == 1) {
812 if (!is_lucent_phy(hp)) {
813 /* Re-enable transceiver, we'll re-enable the transceiver next
814 * tick, then check link state on the following tick.
815 */
816 hp->sw_csconfig |= CSCONFIG_TCVDISAB;
817 happy_meal_tcvr_write(hp, tregs,
818 DP83840_CSCONFIG, hp->sw_csconfig);
819 }
820 restart_timer = 1;
821 break;
822 }
823 if (hp->timer_ticks == 2) {
824 if (!is_lucent_phy(hp)) {
825 hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB);
826 happy_meal_tcvr_write(hp, tregs,
827 DP83840_CSCONFIG, hp->sw_csconfig);
828 }
829 restart_timer = 1;
830 break;
831 }
832 if (hp->sw_bmsr & BMSR_LSTATUS) {
833 /* Force mode selection success. */
834 display_forced_link_mode(hp, tregs);
835 set_happy_link_modes(hp, tregs); /* XXX error? then what? */
836 hp->timer_state = asleep;
837 restart_timer = 0;
838 } else {
839 if (hp->timer_ticks >= 4) { /* 6 seconds or so... */
840 int ret;
841
842 ret = try_next_permutation(hp, tregs);
843 if (ret == -1) {
844 /* Aieee, tried them all, reset the
845 * chip and try all over again.
846 */
847
848 /* Let the user know... */
849 printk(KERN_NOTICE "%s: Link down, cable problem?\n",
850 hp->dev->name);
851
852 ret = happy_meal_init(hp, 0);
853 if (ret) {
854 /* ho hum... */
855 printk(KERN_ERR "%s: Error, cannot re-init the "
856 "Happy Meal.\n", hp->dev->name);
857 }
858 return;
859 }
860 if (!is_lucent_phy(hp)) {
861 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs,
862 DP83840_CSCONFIG);
863 hp->sw_csconfig |= CSCONFIG_TCVDISAB;
864 happy_meal_tcvr_write(hp, tregs,
865 DP83840_CSCONFIG, hp->sw_csconfig);
866 }
867 hp->timer_ticks = 0;
868 restart_timer = 1;
869 } else {
870 restart_timer = 1;
871 }
872 }
873 break;
874
875 case asleep:
876 default:
877 /* Can't happens.... */
878 printk(KERN_ERR "%s: Aieee, link timer is asleep but we got one anyways!\n",
879 hp->dev->name);
880 restart_timer = 0;
881 hp->timer_ticks = 0;
882 hp->timer_state = asleep; /* foo on you */
883 break;
884 };
885
886 if (restart_timer) {
887 hp->happy_timer.expires = jiffies + ((12 * HZ)/10); /* 1.2 sec. */
888 add_timer(&hp->happy_timer);
889 }
890 }
891
892 #define TX_RESET_TRIES 32
893 #define RX_RESET_TRIES 32
894
895 static void happy_meal_tx_reset(struct happy_meal *hp, unsigned long bregs)
896 {
897 int tries = TX_RESET_TRIES;
898
899 HMD(("happy_meal_tx_reset: reset, "));
900
901 /* Would you like to try our SMCC Delux? */
902 hme_write32(hp, bregs + BMAC_TXSWRESET, 0);
903 while ((hme_read32(hp, bregs + BMAC_TXSWRESET) & 1) && --tries)
904 udelay(20);
905
906 /* Lettuce, tomato, buggy hardware (no extra charge)? */
907 if (!tries)
908 printk(KERN_ERR "happy meal: Transceiver BigMac ATTACK!");
909
910 /* Take care. */
911 HMD(("done\n"));
912 }
913
914 static void happy_meal_rx_reset(struct happy_meal *hp, unsigned long bregs)
915 {
916 int tries = RX_RESET_TRIES;
917
918 HMD(("happy_meal_rx_reset: reset, "));
919
920 /* We have a special on GNU/Viking hardware bugs today. */
921 hme_write32(hp, bregs + BMAC_RXSWRESET, 0);
922 while ((hme_read32(hp, bregs + BMAC_RXSWRESET) & 1) && --tries)
923 udelay(20);
924
925 /* Will that be all? */
926 if (!tries)
927 printk(KERN_ERR "happy meal: Receiver BigMac ATTACK!");
928
929 /* Don't forget your vik_1137125_wa. Have a nice day. */
930 HMD(("done\n"));
931 }
932
933 #define STOP_TRIES 16
934
935 static void happy_meal_stop(struct happy_meal *hp, unsigned long gregs)
936 {
937 int tries = STOP_TRIES;
938
939 HMD(("happy_meal_stop: reset, "));
940
941 /* We're consolidating our STB products, it's your lucky day. */
942 hme_write32(hp, gregs + GREG_SWRESET, GREG_RESET_ALL);
943 while (hme_read32(hp, gregs + GREG_SWRESET) && --tries)
944 udelay(20);
945
946 /* Come back next week when we are "Sun Microelectronics". */
947 if (!tries)
948 printk(KERN_ERR "happy meal: Fry guys.");
949
950 /* Remember: "Different name, same old buggy as shit hardware." */
951 HMD(("done\n"));
952 }
953
954 static void happy_meal_get_counters(struct happy_meal *hp, unsigned long bregs)
955 {
956 struct net_device_stats *stats = &hp->net_stats;
957
958 stats->rx_crc_errors += hme_read32(hp, bregs + BMAC_RCRCECTR);
959 hme_write32(hp, bregs + BMAC_RCRCECTR, 0);
960
961 stats->rx_frame_errors += hme_read32(hp, bregs + BMAC_UNALECTR);
962 hme_write32(hp, bregs + BMAC_UNALECTR, 0);
963
964 stats->rx_length_errors += hme_read32(hp, bregs + BMAC_GLECTR);
965 hme_write32(hp, bregs + BMAC_GLECTR, 0);
966
967 stats->tx_aborted_errors += hme_read32(hp, bregs + BMAC_EXCTR);
968
969 stats->collisions +=
970 (hme_read32(hp, bregs + BMAC_EXCTR) +
971 hme_read32(hp, bregs + BMAC_LTCTR));
972 hme_write32(hp, bregs + BMAC_EXCTR, 0);
973 hme_write32(hp, bregs + BMAC_LTCTR, 0);
974 }
975
976 #if 0
977 static void happy_meal_poll_start(struct happy_meal *hp, unsigned long tregs)
978 {
979 u32 tmp;
980 int speed;
981
982 ASD(("happy_meal_poll_start: "));
983 if (!(hp->happy_flags & HFLAG_POLLENABLE)) {
984 HMD(("polling disabled, return\n"));
985 return;
986 }
987
988 /* Start the MIF polling on the external transceiver. */
989 ASD(("polling on, "));
990 tmp = hme_read32(hp, tregs + TCVR_CFG);
991 tmp &= ~(TCV_CFG_PDADDR | TCV_CFG_PREGADDR);
992 tmp |= ((hp->paddr & 0x1f) << 10);
993 tmp |= (TCV_PADDR_ETX << 3);
994 tmp |= TCV_CFG_PENABLE;
995 hme_write32(hp, tregs + TCVR_CFG, tmp);
996
997 /* Let the bits set. */
998 udelay(200);
999
1000 /* We are polling now. */
1001 ASD(("now polling, "));
1002 hp->happy_flags |= HFLAG_POLL;
1003
1004 /* Clear the poll flags, get the basic status as of now. */
1005 hp->poll_flag = 0;
1006 hp->poll_data = hme_read32(hp, tregs + TCVR_STATUS) >> 16;
1007
1008 if (hp->happy_flags & HFLAG_AUTO)
1009 speed = hp->auto_speed;
1010 else
1011 speed = hp->forced_speed;
1012
1013 /* Listen only for the MIF interrupts we want to hear. */
1014 ASD(("mif ints on, "));
1015 if (speed == 100)
1016 hme_write32(hp, tregs + TCVR_IMASK, 0xfffb);
1017 else
1018 hme_write32(hp, tregs + TCVR_IMASK, 0xfff9);
1019 ASD(("done\n"));
1020 }
1021 #endif
1022
1023 static void happy_meal_poll_stop(struct happy_meal *hp, unsigned long tregs)
1024 {
1025 ASD(("happy_meal_poll_stop: "));
1026
1027 /* If polling disabled or not polling already, nothing to do. */
1028 if ((hp->happy_flags & (HFLAG_POLLENABLE | HFLAG_POLL)) !=
1029 (HFLAG_POLLENABLE | HFLAG_POLL)) {
1030 HMD(("not polling, return\n"));
1031 return;
1032 }
1033
1034 /* Shut up the MIF. */
1035 ASD(("were polling, mif ints off, "));
1036 hme_write32(hp, tregs + TCVR_IMASK, 0xffff);
1037
1038 /* Turn off polling. */
1039 ASD(("polling off, "));
1040 hme_write32(hp, tregs + TCVR_CFG,
1041 hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_PENABLE));
1042
1043 /* We are no longer polling. */
1044 hp->happy_flags &= ~(HFLAG_POLL);
1045
1046 /* Let the bits set. */
1047 udelay(200);
1048 ASD(("done\n"));
1049 }
1050
1051 /* Only Sun can take such nice parts and fuck up the programming interface
1052 * like this. Good job guys...
1053 */
1054 #define TCVR_RESET_TRIES 16 /* It should reset quickly */
1055 #define TCVR_UNISOLATE_TRIES 32 /* Dis-isolation can take longer. */
1056
1057 static int happy_meal_tcvr_reset(struct happy_meal *hp, unsigned long tregs)
1058 {
1059 u32 tconfig;
1060 int result, tries = TCVR_RESET_TRIES;
1061
1062 tconfig = hme_read32(hp, tregs + TCVR_CFG);
1063 ASD(("happy_meal_tcvr_reset: tcfg<%08lx> ", tconfig));
1064 if (hp->tcvr_type == external) {
1065 ASD(("external<"));
1066 hme_write32(hp, tregs + TCVR_CFG, tconfig & ~(TCV_CFG_PSELECT));
1067 hp->tcvr_type = internal;
1068 hp->paddr = TCV_PADDR_ITX;
1069 ASD(("ISOLATE,"));
1070 happy_meal_tcvr_write(hp, tregs, MII_BMCR,
1071 (BMCR_LOOPBACK|BMCR_PDOWN|BMCR_ISOLATE));
1072 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1073 if (result == TCVR_FAILURE) {
1074 ASD(("phyread_fail>\n"));
1075 return -1;
1076 }
1077 ASD(("phyread_ok,PSELECT>"));
1078 hme_write32(hp, tregs + TCVR_CFG, tconfig | TCV_CFG_PSELECT);
1079 hp->tcvr_type = external;
1080 hp->paddr = TCV_PADDR_ETX;
1081 } else {
1082 if (tconfig & TCV_CFG_MDIO1) {
1083 ASD(("internal<PSELECT,"));
1084 hme_write32(hp, tregs + TCVR_CFG, (tconfig | TCV_CFG_PSELECT));
1085 ASD(("ISOLATE,"));
1086 happy_meal_tcvr_write(hp, tregs, MII_BMCR,
1087 (BMCR_LOOPBACK|BMCR_PDOWN|BMCR_ISOLATE));
1088 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1089 if (result == TCVR_FAILURE) {
1090 ASD(("phyread_fail>\n"));
1091 return -1;
1092 }
1093 ASD(("phyread_ok,~PSELECT>"));
1094 hme_write32(hp, tregs + TCVR_CFG, (tconfig & ~(TCV_CFG_PSELECT)));
1095 hp->tcvr_type = internal;
1096 hp->paddr = TCV_PADDR_ITX;
1097 }
1098 }
1099
1100 ASD(("BMCR_RESET "));
1101 happy_meal_tcvr_write(hp, tregs, MII_BMCR, BMCR_RESET);
1102
1103 while (--tries) {
1104 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1105 if (result == TCVR_FAILURE)
1106 return -1;
1107 hp->sw_bmcr = result;
1108 if (!(result & BMCR_RESET))
1109 break;
1110 udelay(20);
1111 }
1112 if (!tries) {
1113 ASD(("BMCR RESET FAILED!\n"));
1114 return -1;
1115 }
1116 ASD(("RESET_OK\n"));
1117
1118 /* Get fresh copies of the PHY registers. */
1119 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
1120 hp->sw_physid1 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID1);
1121 hp->sw_physid2 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID2);
1122 hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, MII_ADVERTISE);
1123
1124 ASD(("UNISOLATE"));
1125 hp->sw_bmcr &= ~(BMCR_ISOLATE);
1126 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1127
1128 tries = TCVR_UNISOLATE_TRIES;
1129 while (--tries) {
1130 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1131 if (result == TCVR_FAILURE)
1132 return -1;
1133 if (!(result & BMCR_ISOLATE))
1134 break;
1135 udelay(20);
1136 }
1137 if (!tries) {
1138 ASD((" FAILED!\n"));
1139 return -1;
1140 }
1141 ASD((" SUCCESS and CSCONFIG_DFBYPASS\n"));
1142 if (!is_lucent_phy(hp)) {
1143 result = happy_meal_tcvr_read(hp, tregs,
1144 DP83840_CSCONFIG);
1145 happy_meal_tcvr_write(hp, tregs,
1146 DP83840_CSCONFIG, (result | CSCONFIG_DFBYPASS));
1147 }
1148 return 0;
1149 }
1150
1151 /* Figure out whether we have an internal or external transceiver. */
1152 static void happy_meal_transceiver_check(struct happy_meal *hp, unsigned long tregs)
1153 {
1154 unsigned long tconfig = hme_read32(hp, tregs + TCVR_CFG);
1155
1156 ASD(("happy_meal_transceiver_check: tcfg=%08lx ", tconfig));
1157 if (hp->happy_flags & HFLAG_POLL) {
1158 /* If we are polling, we must stop to get the transceiver type. */
1159 ASD(("<polling> "));
1160 if (hp->tcvr_type == internal) {
1161 if (tconfig & TCV_CFG_MDIO1) {
1162 ASD(("<internal> <poll stop> "));
1163 happy_meal_poll_stop(hp, tregs);
1164 hp->paddr = TCV_PADDR_ETX;
1165 hp->tcvr_type = external;
1166 ASD(("<external>\n"));
1167 tconfig &= ~(TCV_CFG_PENABLE);
1168 tconfig |= TCV_CFG_PSELECT;
1169 hme_write32(hp, tregs + TCVR_CFG, tconfig);
1170 }
1171 } else {
1172 if (hp->tcvr_type == external) {
1173 ASD(("<external> "));
1174 if (!(hme_read32(hp, tregs + TCVR_STATUS) >> 16)) {
1175 ASD(("<poll stop> "));
1176 happy_meal_poll_stop(hp, tregs);
1177 hp->paddr = TCV_PADDR_ITX;
1178 hp->tcvr_type = internal;
1179 ASD(("<internal>\n"));
1180 hme_write32(hp, tregs + TCVR_CFG,
1181 hme_read32(hp, tregs + TCVR_CFG) &
1182 ~(TCV_CFG_PSELECT));
1183 }
1184 ASD(("\n"));
1185 } else {
1186 ASD(("<none>\n"));
1187 }
1188 }
1189 } else {
1190 u32 reread = hme_read32(hp, tregs + TCVR_CFG);
1191
1192 /* Else we can just work off of the MDIO bits. */
1193 ASD(("<not polling> "));
1194 if (reread & TCV_CFG_MDIO1) {
1195 hme_write32(hp, tregs + TCVR_CFG, tconfig | TCV_CFG_PSELECT);
1196 hp->paddr = TCV_PADDR_ETX;
1197 hp->tcvr_type = external;
1198 ASD(("<external>\n"));
1199 } else {
1200 if (reread & TCV_CFG_MDIO0) {
1201 hme_write32(hp, tregs + TCVR_CFG,
1202 tconfig & ~(TCV_CFG_PSELECT));
1203 hp->paddr = TCV_PADDR_ITX;
1204 hp->tcvr_type = internal;
1205 ASD(("<internal>\n"));
1206 } else {
1207 printk(KERN_ERR "happy meal: Transceiver and a coke please.");
1208 hp->tcvr_type = none; /* Grrr... */
1209 ASD(("<none>\n"));
1210 }
1211 }
1212 }
1213 }
1214
1215 /* The receive ring buffers are a bit tricky to get right. Here goes...
1216 *
1217 * The buffers we dma into must be 64 byte aligned. So we use a special
1218 * alloc_skb() routine for the happy meal to allocate 64 bytes more than
1219 * we really need.
1220 *
1221 * We use skb_reserve() to align the data block we get in the skb. We
1222 * also program the etxregs->cfg register to use an offset of 2. This
1223 * imperical constant plus the ethernet header size will always leave
1224 * us with a nicely aligned ip header once we pass things up to the
1225 * protocol layers.
1226 *
1227 * The numbers work out to:
1228 *
1229 * Max ethernet frame size 1518
1230 * Ethernet header size 14
1231 * Happy Meal base offset 2
1232 *
1233 * Say a skb data area is at 0xf001b010, and its size alloced is
1234 * (ETH_FRAME_LEN + 64 + 2) = (1514 + 64 + 2) = 1580 bytes.
1235 *
1236 * First our alloc_skb() routine aligns the data base to a 64 byte
1237 * boundry. We now have 0xf001b040 as our skb data address. We
1238 * plug this into the receive descriptor address.
1239 *
1240 * Next, we skb_reserve() 2 bytes to account for the Happy Meal offset.
1241 * So now the data we will end up looking at starts at 0xf001b042. When
1242 * the packet arrives, we will check out the size received and subtract
1243 * this from the skb->length. Then we just pass the packet up to the
1244 * protocols as is, and allocate a new skb to replace this slot we have
1245 * just received from.
1246 *
1247 * The ethernet layer will strip the ether header from the front of the
1248 * skb we just sent to it, this leaves us with the ip header sitting
1249 * nicely aligned at 0xf001b050. Also, for tcp and udp packets the
1250 * Happy Meal has even checksummed the tcp/udp data for us. The 16
1251 * bit checksum is obtained from the low bits of the receive descriptor
1252 * flags, thus:
1253 *
1254 * skb->csum = rxd->rx_flags & 0xffff;
1255 * skb->ip_summed = CHECKSUM_HW;
1256 *
1257 * before sending off the skb to the protocols, and we are good as gold.
1258 */
1259 static void happy_meal_clean_rings(struct happy_meal *hp)
1260 {
1261 int i;
1262
1263 for (i = 0; i < RX_RING_SIZE; i++) {
1264 if (hp->rx_skbs[i] != NULL) {
1265 struct sk_buff *skb = hp->rx_skbs[i];
1266 struct happy_meal_rxd *rxd;
1267 u32 dma_addr;
1268
1269 rxd = &hp->happy_block->happy_meal_rxd[i];
1270 dma_addr = hme_read_desc32(hp, &rxd->rx_addr);
1271 hme_dma_unmap(hp, dma_addr, RX_BUF_ALLOC_SIZE, DMA_FROMDEVICE);
1272 dev_kfree_skb_any(skb);
1273 hp->rx_skbs[i] = NULL;
1274 }
1275 }
1276
1277 for (i = 0; i < TX_RING_SIZE; i++) {
1278 if (hp->tx_skbs[i] != NULL) {
1279 struct sk_buff *skb = hp->tx_skbs[i];
1280 struct happy_meal_txd *txd;
1281 u32 dma_addr;
1282 int frag;
1283
1284 hp->tx_skbs[i] = NULL;
1285
1286 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1287 txd = &hp->happy_block->happy_meal_txd[i];
1288 dma_addr = hme_read_desc32(hp, &txd->tx_addr);
1289 hme_dma_unmap(hp, dma_addr,
1290 (hme_read_desc32(hp, &txd->tx_flags)
1291 & TXFLAG_SIZE),
1292 DMA_TODEVICE);
1293
1294 if (frag != skb_shinfo(skb)->nr_frags)
1295 i++;
1296 }
1297
1298 dev_kfree_skb_any(skb);
1299 }
1300 }
1301 }
1302
1303 static void happy_meal_init_rings(struct happy_meal *hp, int from_irq)
1304 {
1305 struct hmeal_init_block *hb = hp->happy_block;
1306 struct net_device *dev = hp->dev;
1307 int i, gfp_flags = GFP_KERNEL;
1308
1309 if (from_irq || in_interrupt())
1310 gfp_flags = GFP_ATOMIC;
1311
1312 HMD(("happy_meal_init_rings: counters to zero, "));
1313 hp->rx_new = hp->rx_old = hp->tx_new = hp->tx_old = 0;
1314
1315 /* Free any skippy bufs left around in the rings. */
1316 HMD(("clean, "));
1317 happy_meal_clean_rings(hp);
1318
1319 /* Now get new skippy bufs for the receive ring. */
1320 HMD(("init rxring, "));
1321 for (i = 0; i < RX_RING_SIZE; i++) {
1322 struct sk_buff *skb;
1323
1324 skb = happy_meal_alloc_skb(RX_BUF_ALLOC_SIZE, gfp_flags);
1325 if (!skb) {
1326 hme_write_rxd(hp, &hb->happy_meal_rxd[i], 0, 0);
1327 continue;
1328 }
1329 hp->rx_skbs[i] = skb;
1330 skb->dev = dev;
1331
1332 /* Because we reserve afterwards. */
1333 skb_put(skb, (ETH_FRAME_LEN + RX_OFFSET));
1334 hme_write_rxd(hp, &hb->happy_meal_rxd[i],
1335 (RXFLAG_OWN | ((RX_BUF_ALLOC_SIZE - RX_OFFSET) << 16)),
1336 hme_dma_map(hp, skb->data, RX_BUF_ALLOC_SIZE, DMA_FROMDEVICE));
1337 skb_reserve(skb, RX_OFFSET);
1338 }
1339
1340 HMD(("init txring, "));
1341 for (i = 0; i < TX_RING_SIZE; i++)
1342 hme_write_txd(hp, &hb->happy_meal_txd[i], 0, 0);
1343
1344 HMD(("done\n"));
1345 }
1346
1347 static void happy_meal_begin_auto_negotiation(struct happy_meal *hp,
1348 unsigned long tregs,
1349 struct ethtool_cmd *ep)
1350 {
1351 int timeout;
1352
1353 /* Read all of the registers we are interested in now. */
1354 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
1355 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1356 hp->sw_physid1 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID1);
1357 hp->sw_physid2 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID2);
1358
1359 /* XXX Check BMSR_ANEGCAPABLE, should not be necessary though. */
1360
1361 hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, MII_ADVERTISE);
1362 if (ep == NULL || ep->autoneg == AUTONEG_ENABLE) {
1363 /* Advertise everything we can support. */
1364 if (hp->sw_bmsr & BMSR_10HALF)
1365 hp->sw_advertise |= (ADVERTISE_10HALF);
1366 else
1367 hp->sw_advertise &= ~(ADVERTISE_10HALF);
1368
1369 if (hp->sw_bmsr & BMSR_10FULL)
1370 hp->sw_advertise |= (ADVERTISE_10FULL);
1371 else
1372 hp->sw_advertise &= ~(ADVERTISE_10FULL);
1373 if (hp->sw_bmsr & BMSR_100HALF)
1374 hp->sw_advertise |= (ADVERTISE_100HALF);
1375 else
1376 hp->sw_advertise &= ~(ADVERTISE_100HALF);
1377 if (hp->sw_bmsr & BMSR_100FULL)
1378 hp->sw_advertise |= (ADVERTISE_100FULL);
1379 else
1380 hp->sw_advertise &= ~(ADVERTISE_100FULL);
1381 happy_meal_tcvr_write(hp, tregs, MII_ADVERTISE, hp->sw_advertise);
1382
1383 /* XXX Currently no Happy Meal cards I know off support 100BaseT4,
1384 * XXX and this is because the DP83840 does not support it, changes
1385 * XXX would need to be made to the tx/rx logic in the driver as well
1386 * XXX so I completely skip checking for it in the BMSR for now.
1387 */
1388
1389 #ifdef AUTO_SWITCH_DEBUG
1390 ASD(("%s: Advertising [ ", hp->dev->name));
1391 if (hp->sw_advertise & ADVERTISE_10HALF)
1392 ASD(("10H "));
1393 if (hp->sw_advertise & ADVERTISE_10FULL)
1394 ASD(("10F "));
1395 if (hp->sw_advertise & ADVERTISE_100HALF)
1396 ASD(("100H "));
1397 if (hp->sw_advertise & ADVERTISE_100FULL)
1398 ASD(("100F "));
1399 #endif
1400
1401 /* Enable Auto-Negotiation, this is usually on already... */
1402 hp->sw_bmcr |= BMCR_ANENABLE;
1403 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1404
1405 /* Restart it to make sure it is going. */
1406 hp->sw_bmcr |= BMCR_ANRESTART;
1407 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1408
1409 /* BMCR_ANRESTART self clears when the process has begun. */
1410
1411 timeout = 64; /* More than enough. */
1412 while (--timeout) {
1413 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1414 if (!(hp->sw_bmcr & BMCR_ANRESTART))
1415 break; /* got it. */
1416 udelay(10);
1417 }
1418 if (!timeout) {
1419 printk(KERN_ERR "%s: Happy Meal would not start auto negotiation "
1420 "BMCR=0x%04x\n", hp->dev->name, hp->sw_bmcr);
1421 printk(KERN_NOTICE "%s: Performing force link detection.\n",
1422 hp->dev->name);
1423 goto force_link;
1424 } else {
1425 hp->timer_state = arbwait;
1426 }
1427 } else {
1428 force_link:
1429 /* Force the link up, trying first a particular mode.
1430 * Either we are here at the request of ethtool or
1431 * because the Happy Meal would not start to autoneg.
1432 */
1433
1434 /* Disable auto-negotiation in BMCR, enable the duplex and
1435 * speed setting, init the timer state machine, and fire it off.
1436 */
1437 if (ep == NULL || ep->autoneg == AUTONEG_ENABLE) {
1438 hp->sw_bmcr = BMCR_SPEED100;
1439 } else {
1440 if (ep->speed == SPEED_100)
1441 hp->sw_bmcr = BMCR_SPEED100;
1442 else
1443 hp->sw_bmcr = 0;
1444 if (ep->duplex == DUPLEX_FULL)
1445 hp->sw_bmcr |= BMCR_FULLDPLX;
1446 }
1447 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1448
1449 if (!is_lucent_phy(hp)) {
1450 /* OK, seems we need do disable the transceiver for the first
1451 * tick to make sure we get an accurate link state at the
1452 * second tick.
1453 */
1454 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs,
1455 DP83840_CSCONFIG);
1456 hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB);
1457 happy_meal_tcvr_write(hp, tregs, DP83840_CSCONFIG,
1458 hp->sw_csconfig);
1459 }
1460 hp->timer_state = ltrywait;
1461 }
1462
1463 hp->timer_ticks = 0;
1464 hp->happy_timer.expires = jiffies + (12 * HZ)/10; /* 1.2 sec. */
1465 hp->happy_timer.data = (unsigned long) hp;
1466 hp->happy_timer.function = &happy_meal_timer;
1467 add_timer(&hp->happy_timer);
1468 }
1469
1470 #define CRC_POLYNOMIAL_BE 0x04c11db7UL /* Ethernet CRC, big endian */
1471 #define CRC_POLYNOMIAL_LE 0xedb88320UL /* Ethernet CRC, little endian */
1472
1473 static int happy_meal_init(struct happy_meal *hp, int from_irq)
1474 {
1475 unsigned long gregs = hp->gregs;
1476 unsigned long etxregs = hp->etxregs;
1477 unsigned long erxregs = hp->erxregs;
1478 unsigned long bregs = hp->bigmacregs;
1479 unsigned long tregs = hp->tcvregs;
1480 u32 regtmp, rxcfg;
1481 unsigned char *e = &hp->dev->dev_addr[0];
1482
1483 /* If auto-negotiation timer is running, kill it. */
1484 del_timer(&hp->happy_timer);
1485
1486 HMD(("happy_meal_init: happy_flags[%08x] ",
1487 hp->happy_flags));
1488 if (!(hp->happy_flags & HFLAG_INIT)) {
1489 HMD(("set HFLAG_INIT, "));
1490 hp->happy_flags |= HFLAG_INIT;
1491 happy_meal_get_counters(hp, bregs);
1492 }
1493
1494 /* Stop polling. */
1495 HMD(("to happy_meal_poll_stop\n"));
1496 happy_meal_poll_stop(hp, tregs);
1497
1498 /* Stop transmitter and receiver. */
1499 HMD(("happy_meal_init: to happy_meal_stop\n"));
1500 happy_meal_stop(hp, gregs);
1501
1502 /* Alloc and reset the tx/rx descriptor chains. */
1503 HMD(("happy_meal_init: to happy_meal_init_rings\n"));
1504 happy_meal_init_rings(hp, from_irq);
1505
1506 /* Shut up the MIF. */
1507 HMD(("happy_meal_init: Disable all MIF irqs (old[%08x]), ",
1508 hme_read32(hp, tregs + TCVR_IMASK)));
1509 hme_write32(hp, tregs + TCVR_IMASK, 0xffff);
1510
1511 /* See if we can enable the MIF frame on this card to speak to the DP83840. */
1512 if (hp->happy_flags & HFLAG_FENABLE) {
1513 HMD(("use frame old[%08x], ",
1514 hme_read32(hp, tregs + TCVR_CFG)));
1515 hme_write32(hp, tregs + TCVR_CFG,
1516 hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_BENABLE));
1517 } else {
1518 HMD(("use bitbang old[%08x], ",
1519 hme_read32(hp, tregs + TCVR_CFG)));
1520 hme_write32(hp, tregs + TCVR_CFG,
1521 hme_read32(hp, tregs + TCVR_CFG) | TCV_CFG_BENABLE);
1522 }
1523
1524 /* Check the state of the transceiver. */
1525 HMD(("to happy_meal_transceiver_check\n"));
1526 happy_meal_transceiver_check(hp, tregs);
1527
1528 /* Put the Big Mac into a sane state. */
1529 HMD(("happy_meal_init: "));
1530 switch(hp->tcvr_type) {
1531 case none:
1532 /* Cannot operate if we don't know the transceiver type! */
1533 HMD(("AAIEEE no transceiver type, EAGAIN"));
1534 return -EAGAIN;
1535
1536 case internal:
1537 /* Using the MII buffers. */
1538 HMD(("internal, using MII, "));
1539 hme_write32(hp, bregs + BMAC_XIFCFG, 0);
1540 break;
1541
1542 case external:
1543 /* Not using the MII, disable it. */
1544 HMD(("external, disable MII, "));
1545 hme_write32(hp, bregs + BMAC_XIFCFG, BIGMAC_XCFG_MIIDISAB);
1546 break;
1547 };
1548
1549 if (happy_meal_tcvr_reset(hp, tregs))
1550 return -EAGAIN;
1551
1552 /* Reset the Happy Meal Big Mac transceiver and the receiver. */
1553 HMD(("tx/rx reset, "));
1554 happy_meal_tx_reset(hp, bregs);
1555 happy_meal_rx_reset(hp, bregs);
1556
1557 /* Set jam size and inter-packet gaps to reasonable defaults. */
1558 HMD(("jsize/ipg1/ipg2, "));
1559 hme_write32(hp, bregs + BMAC_JSIZE, DEFAULT_JAMSIZE);
1560 hme_write32(hp, bregs + BMAC_IGAP1, DEFAULT_IPG1);
1561 hme_write32(hp, bregs + BMAC_IGAP2, DEFAULT_IPG2);
1562
1563 /* Load up the MAC address and random seed. */
1564 HMD(("rseed/macaddr, "));
1565
1566 /* The docs recommend to use the 10LSB of our MAC here. */
1567 hme_write32(hp, bregs + BMAC_RSEED, ((e[5] | e[4]<<8)&0x3ff));
1568
1569 hme_write32(hp, bregs + BMAC_MACADDR2, ((e[4] << 8) | e[5]));
1570 hme_write32(hp, bregs + BMAC_MACADDR1, ((e[2] << 8) | e[3]));
1571 hme_write32(hp, bregs + BMAC_MACADDR0, ((e[0] << 8) | e[1]));
1572
1573 HMD(("htable, "));
1574 if ((hp->dev->flags & IFF_ALLMULTI) ||
1575 (hp->dev->mc_count > 64)) {
1576 hme_write32(hp, bregs + BMAC_HTABLE0, 0xffff);
1577 hme_write32(hp, bregs + BMAC_HTABLE1, 0xffff);
1578 hme_write32(hp, bregs + BMAC_HTABLE2, 0xffff);
1579 hme_write32(hp, bregs + BMAC_HTABLE3, 0xffff);
1580 } else if ((hp->dev->flags & IFF_PROMISC) == 0) {
1581 u16 hash_table[4];
1582 struct dev_mc_list *dmi = hp->dev->mc_list;
1583 char *addrs;
1584 int i, j, bit, byte;
1585 u32 crc, poly = CRC_POLYNOMIAL_LE;
1586
1587 for (i = 0; i < 4; i++)
1588 hash_table[i] = 0;
1589
1590 for (i = 0; i < hp->dev->mc_count; i++) {
1591 addrs = dmi->dmi_addr;
1592 dmi = dmi->next;
1593
1594 if (!(*addrs & 1))
1595 continue;
1596
1597 crc = 0xffffffffU;
1598 for (byte = 0; byte < 6; byte++) {
1599 for (bit = *addrs++, j = 0; j < 8; j++, bit >>= 1) {
1600 int test;
1601
1602 test = ((bit ^ crc) & 0x01);
1603 crc >>= 1;
1604 if (test)
1605 crc = crc ^ poly;
1606 }
1607 }
1608 crc >>= 26;
1609 hash_table[crc >> 4] |= 1 << (crc & 0xf);
1610 }
1611 hme_write32(hp, bregs + BMAC_HTABLE0, hash_table[0]);
1612 hme_write32(hp, bregs + BMAC_HTABLE1, hash_table[1]);
1613 hme_write32(hp, bregs + BMAC_HTABLE2, hash_table[2]);
1614 hme_write32(hp, bregs + BMAC_HTABLE3, hash_table[3]);
1615 } else {
1616 hme_write32(hp, bregs + BMAC_HTABLE3, 0);
1617 hme_write32(hp, bregs + BMAC_HTABLE2, 0);
1618 hme_write32(hp, bregs + BMAC_HTABLE1, 0);
1619 hme_write32(hp, bregs + BMAC_HTABLE0, 0);
1620 }
1621
1622 /* Set the RX and TX ring ptrs. */
1623 HMD(("ring ptrs rxr[%08x] txr[%08x]\n",
1624 (hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)),
1625 (hp->hblock_dvma + hblock_offset(happy_meal_txd, 0))));
1626 hme_write32(hp, erxregs + ERX_RING,
1627 (hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)));
1628 hme_write32(hp, etxregs + ETX_RING,
1629 (hp->hblock_dvma + hblock_offset(happy_meal_txd, 0)));
1630
1631 /* Set the supported burst sizes. */
1632 HMD(("happy_meal_init: old[%08x] bursts<",
1633 hme_read32(hp, gregs + GREG_CFG)));
1634
1635 #ifndef __sparc__
1636 /* It is always PCI and can handle 64byte bursts. */
1637 hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST64);
1638 #else
1639 if ((hp->happy_bursts & DMA_BURST64) &&
1640 ((hp->happy_flags & HFLAG_PCI) != 0
1641 #ifdef CONFIG_SBUS
1642 || sbus_can_burst64(hp->happy_dev)
1643 #endif
1644 || 0)) {
1645 u32 gcfg = GREG_CFG_BURST64;
1646
1647 /* I have no idea if I should set the extended
1648 * transfer mode bit for Cheerio, so for now I
1649 * do not. -DaveM
1650 */
1651 #ifdef CONFIG_SBUS
1652 if ((hp->happy_flags & HFLAG_PCI) == 0 &&
1653 sbus_can_dma_64bit(hp->happy_dev)) {
1654 sbus_set_sbus64(hp->happy_dev,
1655 hp->happy_bursts);
1656 gcfg |= GREG_CFG_64BIT;
1657 }
1658 #endif
1659
1660 HMD(("64>"));
1661 hme_write32(hp, gregs + GREG_CFG, gcfg);
1662 } else if (hp->happy_bursts & DMA_BURST32) {
1663 HMD(("32>"));
1664 hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST32);
1665 } else if (hp->happy_bursts & DMA_BURST16) {
1666 HMD(("16>"));
1667 hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST16);
1668 } else {
1669 HMD(("XXX>"));
1670 hme_write32(hp, gregs + GREG_CFG, 0);
1671 }
1672 #endif /* __sparc__ */
1673
1674 /* Turn off interrupts we do not want to hear. */
1675 HMD((", enable global interrupts, "));
1676 hme_write32(hp, gregs + GREG_IMASK,
1677 (GREG_IMASK_GOTFRAME | GREG_IMASK_RCNTEXP |
1678 GREG_IMASK_SENTFRAME | GREG_IMASK_TXPERR));
1679
1680 /* Set the transmit ring buffer size. */
1681 HMD(("tx rsize=%d oreg[%08x], ", (int)TX_RING_SIZE,
1682 hme_read32(hp, etxregs + ETX_RSIZE)));
1683 hme_write32(hp, etxregs + ETX_RSIZE, (TX_RING_SIZE >> ETX_RSIZE_SHIFT) - 1);
1684
1685 /* Enable transmitter DVMA. */
1686 HMD(("tx dma enable old[%08x], ",
1687 hme_read32(hp, etxregs + ETX_CFG)));
1688 hme_write32(hp, etxregs + ETX_CFG,
1689 hme_read32(hp, etxregs + ETX_CFG) | ETX_CFG_DMAENABLE);
1690
1691 /* This chip really rots, for the receiver sometimes when you
1692 * write to it's control registers not all the bits get there
1693 * properly. I cannot think of a sane way to provide complete
1694 * coverage for this hardware bug yet.
1695 */
1696 HMD(("erx regs bug old[%08x]\n",
1697 hme_read32(hp, erxregs + ERX_CFG)));
1698 hme_write32(hp, erxregs + ERX_CFG, ERX_CFG_DEFAULT(RX_OFFSET));
1699 regtmp = hme_read32(hp, erxregs + ERX_CFG);
1700 hme_write32(hp, erxregs + ERX_CFG, ERX_CFG_DEFAULT(RX_OFFSET));
1701 if (hme_read32(hp, erxregs + ERX_CFG) != ERX_CFG_DEFAULT(RX_OFFSET)) {
1702 printk(KERN_ERR "happy meal: Eieee, rx config register gets greasy fries.\n");
1703 printk(KERN_ERR "happy meal: Trying to set %08x, reread gives %08x\n",
1704 ERX_CFG_DEFAULT(RX_OFFSET), regtmp);
1705 /* XXX Should return failure here... */
1706 }
1707
1708 /* Enable Big Mac hash table filter. */
1709 HMD(("happy_meal_init: enable hash rx_cfg_old[%08x], ",
1710 hme_read32(hp, bregs + BMAC_RXCFG)));
1711 rxcfg = BIGMAC_RXCFG_HENABLE;
1712 if (hp->dev->flags & IFF_PROMISC)
1713 rxcfg |= BIGMAC_RXCFG_PMISC;
1714 hme_write32(hp, bregs + BMAC_RXCFG, rxcfg);
1715
1716 /* Let the bits settle in the chip. */
1717 udelay(10);
1718
1719 /* Ok, configure the Big Mac transmitter. */
1720 HMD(("BIGMAC init, "));
1721 regtmp = 0;
1722 if (hp->happy_flags & HFLAG_FULL)
1723 regtmp |= BIGMAC_TXCFG_FULLDPLX;
1724 hme_write32(hp, bregs + BMAC_TXCFG, regtmp | BIGMAC_TXCFG_DGIVEUP);
1725
1726 /* Enable the output drivers no matter what. */
1727 regtmp = BIGMAC_XCFG_ODENABLE;
1728
1729 /* If card can do lance mode, enable it. */
1730 if (hp->happy_flags & HFLAG_LANCE)
1731 regtmp |= (DEFAULT_IPG0 << 5) | BIGMAC_XCFG_LANCE;
1732
1733 /* Disable the MII buffers if using external transceiver. */
1734 if (hp->tcvr_type == external)
1735 regtmp |= BIGMAC_XCFG_MIIDISAB;
1736
1737 HMD(("XIF config old[%08x], ",
1738 hme_read32(hp, bregs + BMAC_XIFCFG)));
1739 hme_write32(hp, bregs + BMAC_XIFCFG, regtmp);
1740
1741 /* Start things up. */
1742 HMD(("tx old[%08x] and rx [%08x] ON!\n",
1743 hme_read32(hp, bregs + BMAC_TXCFG),
1744 hme_read32(hp, bregs + BMAC_RXCFG)));
1745 hme_write32(hp, bregs + BMAC_TXCFG,
1746 hme_read32(hp, bregs + BMAC_TXCFG) | BIGMAC_TXCFG_ENABLE);
1747 hme_write32(hp, bregs + BMAC_RXCFG,
1748 hme_read32(hp, bregs + BMAC_RXCFG) | BIGMAC_RXCFG_ENABLE);
1749
1750 /* Get the autonegotiation started, and the watch timer ticking. */
1751 happy_meal_begin_auto_negotiation(hp, tregs, NULL);
1752
1753 /* Success. */
1754 return 0;
1755 }
1756
1757 static void happy_meal_set_initial_advertisement(struct happy_meal *hp)
1758 {
1759 unsigned long tregs = hp->tcvregs;
1760 unsigned long bregs = hp->bigmacregs;
1761 unsigned long gregs = hp->gregs;
1762
1763 happy_meal_stop(hp, gregs);
1764 hme_write32(hp, tregs + TCVR_IMASK, 0xffff);
1765 if (hp->happy_flags & HFLAG_FENABLE)
1766 hme_write32(hp, tregs + TCVR_CFG,
1767 hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_BENABLE));
1768 else
1769 hme_write32(hp, tregs + TCVR_CFG,
1770 hme_read32(hp, tregs + TCVR_CFG) | TCV_CFG_BENABLE);
1771 happy_meal_transceiver_check(hp, tregs);
1772 switch(hp->tcvr_type) {
1773 case none:
1774 return;
1775 case internal:
1776 hme_write32(hp, bregs + BMAC_XIFCFG, 0);
1777 break;
1778 case external:
1779 hme_write32(hp, bregs + BMAC_XIFCFG, BIGMAC_XCFG_MIIDISAB);
1780 break;
1781 };
1782 if (happy_meal_tcvr_reset(hp, tregs))
1783 return;
1784
1785 /* Latch PHY registers as of now. */
1786 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
1787 hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, MII_ADVERTISE);
1788
1789 /* Advertise everything we can support. */
1790 if (hp->sw_bmsr & BMSR_10HALF)
1791 hp->sw_advertise |= (ADVERTISE_10HALF);
1792 else
1793 hp->sw_advertise &= ~(ADVERTISE_10HALF);
1794
1795 if (hp->sw_bmsr & BMSR_10FULL)
1796 hp->sw_advertise |= (ADVERTISE_10FULL);
1797 else
1798 hp->sw_advertise &= ~(ADVERTISE_10FULL);
1799 if (hp->sw_bmsr & BMSR_100HALF)
1800 hp->sw_advertise |= (ADVERTISE_100HALF);
1801 else
1802 hp->sw_advertise &= ~(ADVERTISE_100HALF);
1803 if (hp->sw_bmsr & BMSR_100FULL)
1804 hp->sw_advertise |= (ADVERTISE_100FULL);
1805 else
1806 hp->sw_advertise &= ~(ADVERTISE_100FULL);
1807
1808 /* Update the PHY advertisement register. */
1809 happy_meal_tcvr_write(hp, tregs, MII_ADVERTISE, hp->sw_advertise);
1810 }
1811
1812 /* Once status is latched (by happy_meal_interrupt) it is cleared by
1813 * the hardware, so we cannot re-read it and get a correct value.
1814 */
1815 static int happy_meal_is_not_so_happy(struct happy_meal *hp, u32 status)
1816 {
1817 int reset = 0;
1818
1819 /* Only print messages for non-counter related interrupts. */
1820 if (status & (GREG_STAT_STSTERR | GREG_STAT_TFIFO_UND |
1821 GREG_STAT_MAXPKTERR | GREG_STAT_RXERR |
1822 GREG_STAT_RXPERR | GREG_STAT_RXTERR | GREG_STAT_EOPERR |
1823 GREG_STAT_MIFIRQ | GREG_STAT_TXEACK | GREG_STAT_TXLERR |
1824 GREG_STAT_TXPERR | GREG_STAT_TXTERR | GREG_STAT_SLVERR |
1825 GREG_STAT_SLVPERR))
1826 printk(KERN_ERR "%s: Error interrupt for happy meal, status = %08x\n",
1827 hp->dev->name, status);
1828
1829 if (status & GREG_STAT_RFIFOVF) {
1830 /* Receive FIFO overflow is harmless and the hardware will take
1831 care of it, just some packets are lost. Who cares. */
1832 printk(KERN_DEBUG "%s: Happy Meal receive FIFO overflow.\n", hp->dev->name);
1833 }
1834
1835 if (status & GREG_STAT_STSTERR) {
1836 /* BigMAC SQE link test failed. */
1837 printk(KERN_ERR "%s: Happy Meal BigMAC SQE test failed.\n", hp->dev->name);
1838 reset = 1;
1839 }
1840
1841 if (status & GREG_STAT_TFIFO_UND) {
1842 /* Transmit FIFO underrun, again DMA error likely. */
1843 printk(KERN_ERR "%s: Happy Meal transmitter FIFO underrun, DMA error.\n",
1844 hp->dev->name);
1845 reset = 1;
1846 }
1847
1848 if (status & GREG_STAT_MAXPKTERR) {
1849 /* Driver error, tried to transmit something larger
1850 * than ethernet max mtu.
1851 */
1852 printk(KERN_ERR "%s: Happy Meal MAX Packet size error.\n", hp->dev->name);
1853 reset = 1;
1854 }
1855
1856 if (status & GREG_STAT_NORXD) {
1857 /* This is harmless, it just means the system is
1858 * quite loaded and the incoming packet rate was
1859 * faster than the interrupt handler could keep up
1860 * with.
1861 */
1862 printk(KERN_INFO "%s: Happy Meal out of receive "
1863 "descriptors, packet dropped.\n",
1864 hp->dev->name);
1865 }
1866
1867 if (status & (GREG_STAT_RXERR|GREG_STAT_RXPERR|GREG_STAT_RXTERR)) {
1868 /* All sorts of DMA receive errors. */
1869 printk(KERN_ERR "%s: Happy Meal rx DMA errors [ ", hp->dev->name);
1870 if (status & GREG_STAT_RXERR)
1871 printk("GenericError ");
1872 if (status & GREG_STAT_RXPERR)
1873 printk("ParityError ");
1874 if (status & GREG_STAT_RXTERR)
1875 printk("RxTagBotch ");
1876 printk("]\n");
1877 reset = 1;
1878 }
1879
1880 if (status & GREG_STAT_EOPERR) {
1881 /* Driver bug, didn't set EOP bit in tx descriptor given
1882 * to the happy meal.
1883 */
1884 printk(KERN_ERR "%s: EOP not set in happy meal transmit descriptor!\n",
1885 hp->dev->name);
1886 reset = 1;
1887 }
1888
1889 if (status & GREG_STAT_MIFIRQ) {
1890 /* MIF signalled an interrupt, were we polling it? */
1891 printk(KERN_ERR "%s: Happy Meal MIF interrupt.\n", hp->dev->name);
1892 }
1893
1894 if (status &
1895 (GREG_STAT_TXEACK|GREG_STAT_TXLERR|GREG_STAT_TXPERR|GREG_STAT_TXTERR)) {
1896 /* All sorts of transmit DMA errors. */
1897 printk(KERN_ERR "%s: Happy Meal tx DMA errors [ ", hp->dev->name);
1898 if (status & GREG_STAT_TXEACK)
1899 printk("GenericError ");
1900 if (status & GREG_STAT_TXLERR)
1901 printk("LateError ");
1902 if (status & GREG_STAT_TXPERR)
1903 printk("ParityErro ");
1904 if (status & GREG_STAT_TXTERR)
1905 printk("TagBotch ");
1906 printk("]\n");
1907 reset = 1;
1908 }
1909
1910 if (status & (GREG_STAT_SLVERR|GREG_STAT_SLVPERR)) {
1911 /* Bus or parity error when cpu accessed happy meal registers
1912 * or it's internal FIFO's. Should never see this.
1913 */
1914 printk(KERN_ERR "%s: Happy Meal register access SBUS slave (%s) error.\n",
1915 hp->dev->name,
1916 (status & GREG_STAT_SLVPERR) ? "parity" : "generic");
1917 reset = 1;
1918 }
1919
1920 if (reset) {
1921 printk(KERN_NOTICE "%s: Resetting...\n", hp->dev->name);
1922 happy_meal_init(hp, 1);
1923 return 1;
1924 }
1925 return 0;
1926 }
1927
1928 static void happy_meal_mif_interrupt(struct happy_meal *hp)
1929 {
1930 unsigned long tregs = hp->tcvregs;
1931
1932 printk(KERN_INFO "%s: Link status change.\n", hp->dev->name);
1933 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1934 hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, MII_LPA);
1935
1936 /* Use the fastest transmission protocol possible. */
1937 if (hp->sw_lpa & LPA_100FULL) {
1938 printk(KERN_INFO "%s: Switching to 100Mbps at full duplex.", hp->dev->name);
1939 hp->sw_bmcr |= (BMCR_FULLDPLX | BMCR_SPEED100);
1940 } else if (hp->sw_lpa & LPA_100HALF) {
1941 printk(KERN_INFO "%s: Switching to 100MBps at half duplex.", hp->dev->name);
1942 hp->sw_bmcr |= BMCR_SPEED100;
1943 } else if (hp->sw_lpa & LPA_10FULL) {
1944 printk(KERN_INFO "%s: Switching to 10MBps at full duplex.", hp->dev->name);
1945 hp->sw_bmcr |= BMCR_FULLDPLX;
1946 } else {
1947 printk(KERN_INFO "%s: Using 10Mbps at half duplex.", hp->dev->name);
1948 }
1949 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1950
1951 /* Finally stop polling and shut up the MIF. */
1952 happy_meal_poll_stop(hp, tregs);
1953 }
1954
1955 #ifdef TXDEBUG
1956 #define TXD(x) printk x
1957 #else
1958 #define TXD(x)
1959 #endif
1960
1961 static void happy_meal_tx(struct happy_meal *hp)
1962 {
1963 struct happy_meal_txd *txbase = &hp->happy_block->happy_meal_txd[0];
1964 struct happy_meal_txd *this;
1965 struct net_device *dev = hp->dev;
1966 int elem;
1967
1968 spin_lock(&hp->happy_lock);
1969
1970 elem = hp->tx_old;
1971 TXD(("TX<"));
1972 while (elem != hp->tx_new) {
1973 struct sk_buff *skb;
1974 u32 flags, dma_addr, dma_len;
1975 int frag;
1976
1977 TXD(("[%d]", elem));
1978 this = &txbase[elem];
1979 flags = hme_read_desc32(hp, &this->tx_flags);
1980 if (flags & TXFLAG_OWN)
1981 break;
1982 skb = hp->tx_skbs[elem];
1983 if (skb_shinfo(skb)->nr_frags) {
1984 int last;
1985
1986 last = elem + skb_shinfo(skb)->nr_frags;
1987 last &= (TX_RING_SIZE - 1);
1988 flags = hme_read_desc32(hp, &txbase[last].tx_flags);
1989 if (flags & TXFLAG_OWN)
1990 break;
1991 }
1992 hp->tx_skbs[elem] = NULL;
1993 hp->net_stats.tx_bytes += skb->len;
1994
1995 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1996 dma_addr = hme_read_desc32(hp, &this->tx_addr);
1997 dma_len = hme_read_desc32(hp, &this->tx_flags);
1998
1999 dma_len &= TXFLAG_SIZE;
2000 hme_dma_unmap(hp, dma_addr, dma_len, DMA_TODEVICE);
2001
2002 elem = NEXT_TX(elem);
2003 this = &txbase[elem];
2004 }
2005
2006 dev_kfree_skb_irq(skb);
2007 hp->net_stats.tx_packets++;
2008 }
2009 hp->tx_old = elem;
2010 TXD((">"));
2011
2012 if (netif_queue_stopped(dev) &&
2013 TX_BUFFS_AVAIL(hp) > 0)
2014 netif_wake_queue(dev);
2015
2016 spin_unlock(&hp->happy_lock);
2017 }
2018
2019 #ifdef RXDEBUG
2020 #define RXD(x) printk x
2021 #else
2022 #define RXD(x)
2023 #endif
2024
2025 /* Originally I used to handle the allocation failure by just giving back just
2026 * that one ring buffer to the happy meal. Problem is that usually when that
2027 * condition is triggered, the happy meal expects you to do something reasonable
2028 * with all of the packets it has DMA'd in. So now I just drop the entire
2029 * ring when we cannot get a new skb and give them all back to the happy meal,
2030 * maybe things will be "happier" now.
2031 */
2032 static void happy_meal_rx(struct happy_meal *hp, struct net_device *dev)
2033 {
2034 struct happy_meal_rxd *rxbase = &hp->happy_block->happy_meal_rxd[0];
2035 struct happy_meal_rxd *this;
2036 int elem = hp->rx_new, drops = 0;
2037 u32 flags;
2038
2039 RXD(("RX<"));
2040 this = &rxbase[elem];
2041 while (!((flags = hme_read_desc32(hp, &this->rx_flags)) & RXFLAG_OWN)) {
2042 struct sk_buff *skb;
2043 int len = flags >> 16;
2044 u16 csum = flags & RXFLAG_CSUM;
2045 u32 dma_addr = hme_read_desc32(hp, &this->rx_addr);
2046
2047 RXD(("[%d ", elem));
2048
2049 /* Check for errors. */
2050 if ((len < ETH_ZLEN) || (flags & RXFLAG_OVERFLOW)) {
2051 RXD(("ERR(%08x)]", flags));
2052 hp->net_stats.rx_errors++;
2053 if (len < ETH_ZLEN)
2054 hp->net_stats.rx_length_errors++;
2055 if (len & (RXFLAG_OVERFLOW >> 16)) {
2056 hp->net_stats.rx_over_errors++;
2057 hp->net_stats.rx_fifo_errors++;
2058 }
2059
2060 /* Return it to the Happy meal. */
2061 drop_it:
2062 hp->net_stats.rx_dropped++;
2063 hme_write_rxd(hp, this,
2064 (RXFLAG_OWN|((RX_BUF_ALLOC_SIZE-RX_OFFSET)<<16)),
2065 dma_addr);
2066 goto next;
2067 }
2068 skb = hp->rx_skbs[elem];
2069 if (len > RX_COPY_THRESHOLD) {
2070 struct sk_buff *new_skb;
2071
2072 /* Now refill the entry, if we can. */
2073 new_skb = happy_meal_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
2074 if (new_skb == NULL) {
2075 drops++;
2076 goto drop_it;
2077 }
2078 hme_dma_unmap(hp, dma_addr, RX_BUF_ALLOC_SIZE, DMA_FROMDEVICE);
2079 hp->rx_skbs[elem] = new_skb;
2080 new_skb->dev = dev;
2081 skb_put(new_skb, (ETH_FRAME_LEN + RX_OFFSET));
2082 hme_write_rxd(hp, this,
2083 (RXFLAG_OWN|((RX_BUF_ALLOC_SIZE-RX_OFFSET)<<16)),
2084 hme_dma_map(hp, new_skb->data, RX_BUF_ALLOC_SIZE, DMA_FROMDEVICE));
2085 skb_reserve(new_skb, RX_OFFSET);
2086
2087 /* Trim the original skb for the netif. */
2088 skb_trim(skb, len);
2089 } else {
2090 struct sk_buff *copy_skb = dev_alloc_skb(len + 2);
2091
2092 if (copy_skb == NULL) {
2093 drops++;
2094 goto drop_it;
2095 }
2096
2097 copy_skb->dev = dev;
2098 skb_reserve(copy_skb, 2);
2099 skb_put(copy_skb, len);
2100 hme_dma_sync(hp, dma_addr, len, DMA_FROMDEVICE);
2101 memcpy(copy_skb->data, skb->data, len);
2102
2103 /* Reuse original ring buffer. */
2104 hme_write_rxd(hp, this,
2105 (RXFLAG_OWN|((RX_BUF_ALLOC_SIZE-RX_OFFSET)<<16)),
2106 dma_addr);
2107
2108 skb = copy_skb;
2109 }
2110
2111 /* This card is _fucking_ hot... */
2112 skb->csum = ntohs(csum ^ 0xffff);
2113 skb->ip_summed = CHECKSUM_HW;
2114
2115 RXD(("len=%d csum=%4x]", len, csum));
2116 skb->protocol = eth_type_trans(skb, dev);
2117 netif_rx(skb);
2118
2119 dev->last_rx = jiffies;
2120 hp->net_stats.rx_packets++;
2121 hp->net_stats.rx_bytes += len;
2122 next:
2123 elem = NEXT_RX(elem);
2124 this = &rxbase[elem];
2125 }
2126 hp->rx_new = elem;
2127 if (drops)
2128 printk(KERN_INFO "%s: Memory squeeze, deferring packet.\n", hp->dev->name);
2129 RXD((">"));
2130 }
2131
2132 static void happy_meal_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2133 {
2134 struct net_device *dev = (struct net_device *) dev_id;
2135 struct happy_meal *hp = dev->priv;
2136 u32 happy_status = hme_read32(hp, hp->gregs + GREG_STAT);
2137
2138 HMD(("happy_meal_interrupt: status=%08x ", happy_status));
2139
2140 if (happy_status & GREG_STAT_ERRORS) {
2141 HMD(("ERRORS "));
2142 if (happy_meal_is_not_so_happy(hp, /* un- */ happy_status))
2143 return;
2144 }
2145
2146 if (happy_status & GREG_STAT_MIFIRQ) {
2147 HMD(("MIFIRQ "));
2148 happy_meal_mif_interrupt(hp);
2149 }
2150
2151 if (happy_status & GREG_STAT_TXALL) {
2152 HMD(("TXALL "));
2153 happy_meal_tx(hp);
2154 }
2155
2156 if (happy_status & GREG_STAT_RXTOHOST) {
2157 HMD(("RXTOHOST "));
2158 happy_meal_rx(hp, dev);
2159 }
2160
2161 HMD(("done\n"));
2162 }
2163
2164 #ifdef CONFIG_SBUS
2165 static void quattro_sbus_interrupt(int irq, void *cookie, struct pt_regs *ptregs)
2166 {
2167 struct quattro *qp = (struct quattro *) cookie;
2168 int i;
2169
2170 for (i = 0; i < 4; i++) {
2171 struct net_device *dev = qp->happy_meals[i];
2172 struct happy_meal *hp = dev->priv;
2173 u32 happy_status = hme_read32(hp, hp->gregs + GREG_STAT);
2174
2175 HMD(("quattro_interrupt: status=%08x ", happy_status));
2176
2177 if (!(happy_status & (GREG_STAT_ERRORS |
2178 GREG_STAT_MIFIRQ |
2179 GREG_STAT_TXALL |
2180 GREG_STAT_RXTOHOST)))
2181 continue;
2182
2183 if (happy_status & GREG_STAT_ERRORS) {
2184 HMD(("ERRORS "));
2185 if (happy_meal_is_not_so_happy(hp, happy_status))
2186 break;
2187 }
2188
2189 if (happy_status & GREG_STAT_MIFIRQ) {
2190 HMD(("MIFIRQ "));
2191 happy_meal_mif_interrupt(hp);
2192 }
2193
2194 if (happy_status & GREG_STAT_TXALL) {
2195 HMD(("TXALL "));
2196 happy_meal_tx(hp);
2197 }
2198
2199 if (happy_status & GREG_STAT_RXTOHOST) {
2200 HMD(("RXTOHOST "));
2201 happy_meal_rx(hp, dev);
2202 }
2203 }
2204 HMD(("done\n"));
2205 }
2206 #endif
2207
2208 static int happy_meal_open(struct net_device *dev)
2209 {
2210 struct happy_meal *hp = dev->priv;
2211 int res;
2212
2213 HMD(("happy_meal_open: "));
2214
2215 /* On SBUS Quattro QFE cards, all hme interrupts are concentrated
2216 * into a single source which we register handling at probe time.
2217 */
2218 if ((hp->happy_flags & (HFLAG_QUATTRO|HFLAG_PCI)) != HFLAG_QUATTRO) {
2219 if (request_irq(dev->irq, &happy_meal_interrupt,
2220 SA_SHIRQ, "HAPPY MEAL", (void *)dev)) {
2221 HMD(("EAGAIN\n"));
2222 #ifdef __sparc__
2223 printk(KERN_ERR "happy_meal(SBUS): Can't order irq %s to go.\n",
2224 __irq_itoa(dev->irq));
2225 #else
2226 printk(KERN_ERR "happy_meal(SBUS): Can't order irq %d to go.\n",
2227 dev->irq);
2228 #endif
2229
2230 return -EAGAIN;
2231 }
2232 }
2233
2234 HMD(("to happy_meal_init\n"));
2235 res = happy_meal_init(hp, 0);
2236 if (res && ((hp->happy_flags & (HFLAG_QUATTRO|HFLAG_PCI)) != HFLAG_QUATTRO))
2237 free_irq(dev->irq, dev);
2238 return res;
2239 }
2240
2241 static int happy_meal_close(struct net_device *dev)
2242 {
2243 struct happy_meal *hp = dev->priv;
2244
2245 happy_meal_stop(hp, hp->gregs);
2246 happy_meal_clean_rings(hp);
2247
2248 /* If auto-negotiation timer is running, kill it. */
2249 del_timer(&hp->happy_timer);
2250
2251 /* On Quattro QFE cards, all hme interrupts are concentrated
2252 * into a single source which we register handling at probe
2253 * time and never unregister.
2254 */
2255 if ((hp->happy_flags & (HFLAG_QUATTRO|HFLAG_PCI)) != HFLAG_QUATTRO)
2256 free_irq(dev->irq, dev);
2257
2258 return 0;
2259 }
2260
2261 #ifdef SXDEBUG
2262 #define SXD(x) printk x
2263 #else
2264 #define SXD(x)
2265 #endif
2266
2267 #ifdef CONFIG_SBUS
2268 static void happy_meal_tx_timeout(struct net_device *dev)
2269 {
2270 struct happy_meal *hp = dev->priv;
2271
2272 printk (KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
2273 tx_dump_log();
2274 printk (KERN_ERR "%s: Happy Status %08x TX[%08x:%08x]\n", dev->name,
2275 hme_read32(hp, hp->gregs + GREG_STAT),
2276 hme_read32(hp, hp->etxregs + ETX_CFG),
2277 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG));
2278 happy_meal_init(hp, 0);
2279 netif_wake_queue(dev);
2280 }
2281 #endif
2282
2283 static int happy_meal_start_xmit(struct sk_buff *skb, struct net_device *dev)
2284 {
2285 struct happy_meal *hp = dev->priv;
2286 int entry;
2287 u32 tx_flags;
2288
2289 tx_flags = TXFLAG_OWN;
2290 if (skb->ip_summed == CHECKSUM_HW) {
2291 u32 csum_start_off, csum_stuff_off;
2292
2293 csum_start_off = (u32) (skb->h.raw - skb->data);
2294 csum_stuff_off = (u32) ((skb->h.raw + skb->csum) - skb->data);
2295
2296 tx_flags = (TXFLAG_OWN | TXFLAG_CSENABLE |
2297 ((csum_start_off << 14) & TXFLAG_CSBUFBEGIN) |
2298 ((csum_stuff_off << 20) & TXFLAG_CSLOCATION));
2299 }
2300
2301 spin_lock_irq(&hp->happy_lock);
2302
2303 if (TX_BUFFS_AVAIL(hp) <= (skb_shinfo(skb)->nr_frags + 1)) {
2304 netif_stop_queue(dev);
2305 spin_unlock_irq(&hp->happy_lock);
2306 return 1;
2307 }
2308
2309 entry = hp->tx_new;
2310 SXD(("SX<l[%d]e[%d]>", len, entry));
2311 hp->tx_skbs[entry] = skb;
2312
2313 if (skb_shinfo(skb)->nr_frags == 0) {
2314 u32 mapping, len;
2315
2316 len = skb->len;
2317 mapping = hme_dma_map(hp, skb->data, len, DMA_TODEVICE);
2318 tx_flags |= (TXFLAG_SOP | TXFLAG_EOP);
2319 hme_write_txd(hp, &hp->happy_block->happy_meal_txd[entry],
2320 (tx_flags | (len & TXFLAG_SIZE)),
2321 mapping);
2322 entry = NEXT_TX(entry);
2323 } else {
2324 u32 first_len, first_mapping;
2325 int frag, first_entry = entry;
2326
2327 /* We must give this initial chunk to the device last.
2328 * Otherwise we could race with the device.
2329 */
2330 first_len = skb->len - skb->data_len;
2331 first_mapping = hme_dma_map(hp, skb->data, first_len, DMA_TODEVICE);
2332 entry = NEXT_TX(entry);
2333
2334 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
2335 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
2336 u32 len, mapping, this_txflags;
2337
2338 len = this_frag->size;
2339 mapping = hme_dma_map(hp,
2340 ((void *) page_address(this_frag->page) +
2341 this_frag->page_offset),
2342 len, DMA_TODEVICE);
2343 this_txflags = tx_flags;
2344 if (frag == skb_shinfo(skb)->nr_frags - 1)
2345 this_txflags |= TXFLAG_EOP;
2346 hme_write_txd(hp, &hp->happy_block->happy_meal_txd[entry],
2347 (this_txflags | (len & TXFLAG_SIZE)),
2348 mapping);
2349 entry = NEXT_TX(entry);
2350 }
2351 hme_write_txd(hp, &hp->happy_block->happy_meal_txd[first_entry],
2352 (tx_flags | TXFLAG_SOP | (first_len & TXFLAG_SIZE)),
2353 first_mapping);
2354 }
2355
2356 hp->tx_new = entry;
2357
2358 if (TX_BUFFS_AVAIL(hp) <= 0)
2359 netif_stop_queue(dev);
2360
2361 /* Get it going. */
2362 hme_write32(hp, hp->etxregs + ETX_PENDING, ETX_TP_DMAWAKEUP);
2363
2364 spin_unlock_irq(&hp->happy_lock);
2365
2366 dev->trans_start = jiffies;
2367
2368 tx_add_log(hp, TXLOG_ACTION_TXMIT, 0);
2369 return 0;
2370 }
2371
2372 static struct net_device_stats *happy_meal_get_stats(struct net_device *dev)
2373 {
2374 struct happy_meal *hp = dev->priv;
2375
2376 happy_meal_get_counters(hp, hp->bigmacregs);
2377 return &hp->net_stats;
2378 }
2379
2380 static void happy_meal_set_multicast(struct net_device *dev)
2381 {
2382 struct happy_meal *hp = dev->priv;
2383 unsigned long bregs = hp->bigmacregs;
2384 struct dev_mc_list *dmi = dev->mc_list;
2385 char *addrs;
2386 int i, j, bit, byte;
2387 u32 crc, poly = CRC_POLYNOMIAL_LE;
2388
2389 /* Lock out others. */
2390 netif_stop_queue(dev);
2391
2392 if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 64)) {
2393 hme_write32(hp, bregs + BMAC_HTABLE0, 0xffff);
2394 hme_write32(hp, bregs + BMAC_HTABLE1, 0xffff);
2395 hme_write32(hp, bregs + BMAC_HTABLE2, 0xffff);
2396 hme_write32(hp, bregs + BMAC_HTABLE3, 0xffff);
2397 } else if (dev->flags & IFF_PROMISC) {
2398 hme_write32(hp, bregs + BMAC_RXCFG,
2399 hme_read32(hp, bregs + BMAC_RXCFG) | BIGMAC_RXCFG_PMISC);
2400 } else {
2401 u16 hash_table[4];
2402
2403 for (i = 0; i < 4; i++)
2404 hash_table[i] = 0;
2405
2406 for (i = 0; i < dev->mc_count; i++) {
2407 addrs = dmi->dmi_addr;
2408 dmi = dmi->next;
2409
2410 if (!(*addrs & 1))
2411 continue;
2412
2413 crc = 0xffffffffU;
2414 for (byte = 0; byte < 6; byte++) {
2415 for (bit = *addrs++, j = 0; j < 8; j++, bit >>= 1) {
2416 int test;
2417
2418 test = ((bit ^ crc) & 0x01);
2419 crc >>= 1;
2420 if (test)
2421 crc = crc ^ poly;
2422 }
2423 }
2424 crc >>= 26;
2425 hash_table[crc >> 4] |= 1 << (crc & 0xf);
2426 }
2427 hme_write32(hp, bregs + BMAC_HTABLE0, hash_table[0]);
2428 hme_write32(hp, bregs + BMAC_HTABLE1, hash_table[1]);
2429 hme_write32(hp, bregs + BMAC_HTABLE2, hash_table[2]);
2430 hme_write32(hp, bregs + BMAC_HTABLE3, hash_table[3]);
2431 }
2432
2433 /* Let us get going again. */
2434 netif_wake_queue(dev);
2435 }
2436
2437 /* Ethtool support... */
2438 static int happy_meal_ioctl(struct net_device *dev,
2439 struct ifreq *rq, int cmd)
2440 {
2441 struct happy_meal *hp = dev->priv;
2442 struct ethtool_cmd *ep_user = (struct ethtool_cmd *) rq->ifr_data;
2443 struct ethtool_cmd ecmd;
2444
2445 if (cmd != SIOCETHTOOL)
2446 return -EOPNOTSUPP;
2447 if (copy_from_user(&ecmd, ep_user, sizeof(ecmd)))
2448 return -EFAULT;
2449
2450 if (ecmd.cmd == ETHTOOL_GSET) {
2451 ecmd.supported =
2452 (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2453 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2454 SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII);
2455
2456 /* XXX hardcoded stuff for now */
2457 ecmd.port = PORT_TP; /* XXX no MII support */
2458 ecmd.transceiver = XCVR_INTERNAL; /* XXX no external xcvr support */
2459 ecmd.phy_address = 0; /* XXX fixed PHYAD */
2460
2461 /* Record PHY settings. */
2462 hp->sw_bmcr = happy_meal_tcvr_read(hp, hp->tcvregs, MII_BMCR);
2463 hp->sw_lpa = happy_meal_tcvr_read(hp, hp->tcvregs, MII_LPA);
2464 if (hp->sw_bmcr & BMCR_ANENABLE) {
2465 ecmd.autoneg = AUTONEG_ENABLE;
2466 ecmd.speed =
2467 (hp->sw_lpa & (LPA_100HALF | LPA_100FULL)) ?
2468 SPEED_100 : SPEED_10;
2469 if (ecmd.speed == SPEED_100)
2470 ecmd.duplex =
2471 (hp->sw_lpa & (LPA_100FULL)) ?
2472 DUPLEX_FULL : DUPLEX_HALF;
2473 else
2474 ecmd.duplex =
2475 (hp->sw_lpa & (LPA_10FULL)) ?
2476 DUPLEX_FULL : DUPLEX_HALF;
2477 } else {
2478 ecmd.autoneg = AUTONEG_DISABLE;
2479 ecmd.speed =
2480 (hp->sw_bmcr & BMCR_SPEED100) ?
2481 SPEED_100 : SPEED_10;
2482 ecmd.duplex =
2483 (hp->sw_bmcr & BMCR_FULLDPLX) ?
2484 DUPLEX_FULL : DUPLEX_HALF;
2485 }
2486 if (copy_to_user(ep_user, &ecmd, sizeof(ecmd)))
2487 return -EFAULT;
2488 return 0;
2489 } else if (ecmd.cmd == ETHTOOL_SSET) {
2490 if (!capable(CAP_NET_ADMIN))
2491 return -EPERM;
2492
2493 /* Verify the settings we care about. */
2494 if (ecmd.autoneg != AUTONEG_ENABLE &&
2495 ecmd.autoneg != AUTONEG_DISABLE)
2496 return -EINVAL;
2497 if (ecmd.autoneg == AUTONEG_DISABLE &&
2498 ((ecmd.speed != SPEED_100 &&
2499 ecmd.speed != SPEED_10) ||
2500 (ecmd.duplex != DUPLEX_HALF &&
2501 ecmd.duplex != DUPLEX_FULL)))
2502 return -EINVAL;
2503
2504 /* Ok, do it to it. */
2505 del_timer(&hp->happy_timer);
2506 happy_meal_begin_auto_negotiation(hp,
2507 hp->tcvregs,
2508 &ecmd);
2509
2510 return 0;
2511 } else
2512 return -EOPNOTSUPP;
2513 }
2514
2515 static int hme_version_printed;
2516
2517 #ifdef CONFIG_SBUS
2518 void __init quattro_get_ranges(struct quattro *qp)
2519 {
2520 struct sbus_dev *sdev = qp->quattro_dev;
2521 int err;
2522
2523 err = prom_getproperty(sdev->prom_node,
2524 "ranges",
2525 (char *)&qp->ranges[0],
2526 sizeof(qp->ranges));
2527 if (err == 0 || err == -1) {
2528 qp->nranges = 0;
2529 return;
2530 }
2531 qp->nranges = (err / sizeof(struct linux_prom_ranges));
2532 }
2533
2534 static void __init quattro_apply_ranges(struct quattro *qp, struct happy_meal *hp)
2535 {
2536 struct sbus_dev *sdev = hp->happy_dev;
2537 int rng;
2538
2539 for (rng = 0; rng < qp->nranges; rng++) {
2540 struct linux_prom_ranges *rngp = &qp->ranges[rng];
2541 int reg;
2542
2543 for (reg = 0; reg < 5; reg++) {
2544 if (sdev->reg_addrs[reg].which_io ==
2545 rngp->ot_child_space)
2546 break;
2547 }
2548 if (reg == 5)
2549 continue;
2550
2551 sdev->reg_addrs[reg].which_io = rngp->ot_parent_space;
2552 sdev->reg_addrs[reg].phys_addr += rngp->ot_parent_base;
2553 }
2554 }
2555
2556 /* Given a happy meal sbus device, find it's quattro parent.
2557 * If none exist, allocate and return a new one.
2558 *
2559 * Return NULL on failure.
2560 */
2561 static struct quattro * __init quattro_sbus_find(struct sbus_dev *goal_sdev)
2562 {
2563 struct sbus_bus *sbus;
2564 struct sbus_dev *sdev;
2565 struct quattro *qp;
2566 int i;
2567
2568 if (qfe_sbus_list == NULL)
2569 goto found;
2570
2571 for (qp = qfe_sbus_list; qp != NULL; qp = qp->next) {
2572 for (i = 0, sdev = qp->quattro_dev;
2573 (sdev != NULL) && (i < 4);
2574 sdev = sdev->next, i++) {
2575 if (sdev == goal_sdev)
2576 return qp;
2577 }
2578 }
2579 for_each_sbus(sbus) {
2580 for_each_sbusdev(sdev, sbus) {
2581 if (sdev == goal_sdev)
2582 goto found;
2583 }
2584 }
2585
2586 /* Cannot find quattro parent, fail. */
2587 return NULL;
2588
2589 found:
2590 qp = kmalloc(sizeof(struct quattro), GFP_KERNEL);
2591 if (qp != NULL) {
2592 int i;
2593
2594 for (i = 0; i < 4; i++)
2595 qp->happy_meals[i] = NULL;
2596
2597 qp->quattro_dev = goal_sdev;
2598 qp->next = qfe_sbus_list;
2599 qfe_sbus_list = qp;
2600 quattro_get_ranges(qp);
2601 }
2602 return qp;
2603 }
2604
2605 /* After all quattro cards have been probed, we call these functions
2606 * to register the IRQ handlers.
2607 */
2608 static void __init quattro_sbus_register_irqs(void)
2609 {
2610 struct quattro *qp;
2611
2612 for (qp = qfe_sbus_list; qp != NULL; qp = qp->next) {
2613 struct sbus_dev *sdev = qp->quattro_dev;
2614 int err;
2615
2616 err = request_irq(sdev->irqs[0],
2617 quattro_sbus_interrupt,
2618 SA_SHIRQ, "Quattro",
2619 qp);
2620 if (err != 0) {
2621 printk(KERN_ERR "Quattro: Fatal IRQ registery error %d.\n", err);
2622 panic("QFE request irq");
2623 }
2624 }
2625 }
2626 #endif /* CONFIG_SBUS */
2627
2628 #ifdef CONFIG_PCI
2629 static struct quattro * __init quattro_pci_find(struct pci_dev *pdev)
2630 {
2631 struct pci_dev *bdev = pdev->bus->self;
2632 struct quattro *qp;
2633
2634 if (!bdev) return NULL;
2635 for (qp = qfe_pci_list; qp != NULL; qp = qp->next) {
2636 struct pci_dev *qpdev = qp->quattro_dev;
2637
2638 if (qpdev == bdev)
2639 return qp;
2640 }
2641 qp = kmalloc(sizeof(struct quattro), GFP_KERNEL);
2642 if (qp != NULL) {
2643 int i;
2644
2645 for (i = 0; i < 4; i++)
2646 qp->happy_meals[i] = NULL;
2647
2648 qp->quattro_dev = bdev;
2649 qp->next = qfe_pci_list;
2650 qfe_pci_list = qp;
2651
2652 /* No range tricks necessary on PCI. */
2653 qp->nranges = 0;
2654 }
2655 return qp;
2656 }
2657 #endif /* CONFIG_PCI */
2658
2659 #ifdef CONFIG_SBUS
2660 static int __init happy_meal_sbus_init(struct sbus_dev *sdev, int is_qfe)
2661 {
2662 struct quattro *qp = NULL;
2663 struct happy_meal *hp;
2664 struct net_device *dev;
2665 int i, qfe_slot = -1;
2666
2667 if (is_qfe) {
2668 qp = quattro_sbus_find(sdev);
2669 if (qp == NULL)
2670 return -ENODEV;
2671 for (qfe_slot = 0; qfe_slot < 4; qfe_slot++)
2672 if (qp->happy_meals[qfe_slot] == NULL)
2673 break;
2674 if (qfe_slot == 4)
2675 return -ENODEV;
2676 }
2677
2678 dev = init_etherdev(NULL, sizeof(struct happy_meal));
2679 if (!dev)
2680 return -ENOMEM;
2681 SET_MODULE_OWNER(dev);
2682
2683 if (hme_version_printed++ == 0)
2684 printk(KERN_INFO "%s", version);
2685
2686 if (qfe_slot != -1)
2687 printk(KERN_INFO "%s: Quattro HME slot %d (SBUS) 10/100baseT Ethernet ",
2688 dev->name, qfe_slot);
2689 else
2690 printk(KERN_INFO "%s: HAPPY MEAL (SBUS) 10/100baseT Ethernet ",
2691 dev->name);
2692
2693 /* If user did not specify a MAC address specifically, use
2694 * the Quattro local-mac-address property...
2695 */
2696 for (i = 0; i < 6; i++) {
2697 if (macaddr[i] != 0)
2698 break;
2699 }
2700 if (i < 6) { /* a mac address was given */
2701 for (i = 0; i < 6; i++)
2702 dev->dev_addr[i] = macaddr[i];
2703 } else if (qfe_slot != -1 &&
2704 prom_getproplen(sdev->prom_node,
2705 "local-mac-address") == 6) {
2706 prom_getproperty(sdev->prom_node, "local-mac-address",
2707 dev->dev_addr, 6);
2708 } else {
2709 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2710 }
2711
2712 for (i = 0; i < 6; i++)
2713 printk("%2.2x%c",
2714 dev->dev_addr[i], i == 5 ? ' ' : ':');
2715 printk("\n");
2716
2717 hp = dev->priv;
2718 memset(hp, 0, sizeof(*hp));
2719
2720 hp->happy_dev = sdev;
2721
2722 spin_lock_init(&hp->happy_lock);
2723
2724 if (sdev->num_registers != 5) {
2725 printk(KERN_ERR "happymeal: Device does not have 5 regs, it has %d.\n",
2726 sdev->num_registers);
2727 printk(KERN_ERR "happymeal: Would you like that for here or to go?\n");
2728 return -ENODEV;
2729 }
2730
2731 if (qp != NULL) {
2732 hp->qfe_parent = qp;
2733 hp->qfe_ent = qfe_slot;
2734 qp->happy_meals[qfe_slot] = dev;
2735 quattro_apply_ranges(qp, hp);
2736 }
2737
2738 hp->gregs = sbus_ioremap(&sdev->resource[0], 0,
2739 GREG_REG_SIZE, "HME Global Regs");
2740 if (!hp->gregs) {
2741 printk(KERN_ERR "happymeal: Cannot map Happy Meal global registers.\n");
2742 return -ENODEV;
2743 }
2744
2745 hp->etxregs = sbus_ioremap(&sdev->resource[1], 0,
2746 ETX_REG_SIZE, "HME TX Regs");
2747 if (!hp->etxregs) {
2748 printk(KERN_ERR "happymeal: Cannot map Happy Meal MAC Transmit registers.\n");
2749 return -ENODEV;
2750 }
2751
2752 hp->erxregs = sbus_ioremap(&sdev->resource[2], 0,
2753 ERX_REG_SIZE, "HME RX Regs");
2754 if (!hp->erxregs) {
2755 printk(KERN_ERR "happymeal: Cannot map Happy Meal MAC Receive registers.\n");
2756 return -ENODEV;
2757 }
2758
2759 hp->bigmacregs = sbus_ioremap(&sdev->resource[3], 0,
2760 BMAC_REG_SIZE, "HME BIGMAC Regs");
2761 if (!hp->bigmacregs) {
2762 printk(KERN_ERR "happymeal: Cannot map Happy Meal BIGMAC registers.\n");
2763 return -ENODEV;
2764 }
2765
2766 hp->tcvregs = sbus_ioremap(&sdev->resource[4], 0,
2767 TCVR_REG_SIZE, "HME Tranceiver Regs");
2768 if (!hp->tcvregs) {
2769 printk(KERN_ERR "happymeal: Cannot map Happy Meal Tranceiver registers.\n");
2770 return -ENODEV;
2771 }
2772
2773 hp->hm_revision = prom_getintdefault(sdev->prom_node, "hm-rev", 0xff);
2774 if (hp->hm_revision == 0xff)
2775 hp->hm_revision = 0xa0;
2776
2777 /* Now enable the feature flags we can. */
2778 if (hp->hm_revision == 0x20 || hp->hm_revision == 0x21)
2779 hp->happy_flags = HFLAG_20_21;
2780 else if (hp->hm_revision != 0xa0)
2781 hp->happy_flags = HFLAG_NOT_A0;
2782
2783 if (qp != NULL)
2784 hp->happy_flags |= HFLAG_QUATTRO;
2785
2786 /* Get the supported DVMA burst sizes from our Happy SBUS. */
2787 hp->happy_bursts = prom_getintdefault(sdev->bus->prom_node,
2788 "burst-sizes", 0x00);
2789
2790 hp->happy_block = sbus_alloc_consistent(hp->happy_dev,
2791 PAGE_SIZE,
2792 &hp->hblock_dvma);
2793
2794 /* Force check of the link first time we are brought up. */
2795 hp->linkcheck = 0;
2796
2797 /* Force timer state to 'asleep' with count of zero. */
2798 hp->timer_state = asleep;
2799 hp->timer_ticks = 0;
2800
2801 init_timer(&hp->happy_timer);
2802
2803 hp->dev = dev;
2804 dev->open = &happy_meal_open;
2805 dev->stop = &happy_meal_close;
2806 dev->hard_start_xmit = &happy_meal_start_xmit;
2807 dev->get_stats = &happy_meal_get_stats;
2808 dev->set_multicast_list = &happy_meal_set_multicast;
2809 dev->tx_timeout = &happy_meal_tx_timeout;
2810 dev->watchdog_timeo = 5*HZ;
2811 dev->do_ioctl = &happy_meal_ioctl;
2812
2813 /* Happy Meal can do it all... */
2814 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM;
2815
2816 dev->irq = sdev->irqs[0];
2817
2818 #if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
2819 /* Hook up PCI register/dma accessors. */
2820 hp->read_desc32 = sbus_hme_read_desc32;
2821 hp->write_txd = sbus_hme_write_txd;
2822 hp->write_rxd = sbus_hme_write_rxd;
2823 hp->dma_map = (u32 (*)(void *, void *, long, int))sbus_map_single;
2824 hp->dma_unmap = (void (*)(void *, u32, long, int))sbus_unmap_single;
2825 hp->dma_sync = (void (*)(void *, u32, long, int))sbus_dma_sync_single;
2826 hp->read32 = sbus_hme_read32;
2827 hp->write32 = sbus_hme_write32;
2828 #endif
2829
2830 /* Grrr, Happy Meal comes up by default not advertising
2831 * full duplex 100baseT capabilities, fix this.
2832 */
2833 happy_meal_set_initial_advertisement(hp);
2834
2835 ether_setup(dev);
2836
2837 /* We are home free at this point, link us in to the happy
2838 * device list.
2839 */
2840 dev->ifindex = dev_new_index();
2841 hp->next_module = root_happy_dev;
2842 root_happy_dev = hp;
2843
2844 return 0;
2845 }
2846 #endif
2847
2848 #ifdef CONFIG_PCI
2849 static int __init happy_meal_pci_init(struct pci_dev *pdev)
2850 {
2851 struct quattro *qp = NULL;
2852 #ifdef __sparc__
2853 struct pcidev_cookie *pcp;
2854 int node;
2855 #endif
2856 struct happy_meal *hp;
2857 struct net_device *dev;
2858 unsigned long hpreg_base;
2859 int i, qfe_slot = -1;
2860 char prom_name[64];
2861
2862 /* Now make sure pci_dev cookie is there. */
2863 #ifdef __sparc__
2864 pcp = pdev->sysdata;
2865 if (pcp == NULL || pcp->prom_node == -1) {
2866 printk(KERN_ERR "happymeal(PCI): Some PCI device info missing\n");
2867 return -ENODEV;
2868 }
2869 node = pcp->prom_node;
2870
2871 prom_getstring(node, "name", prom_name, sizeof(prom_name));
2872 #else
2873 /* This needs to be corrected... -DaveM */
2874 strcpy(prom_name, "qfe");
2875 #endif
2876
2877 if (!strcmp(prom_name, "SUNW,qfe") || !strcmp(prom_name, "qfe")) {
2878 qp = quattro_pci_find(pdev);
2879 if (qp == NULL)
2880 return -ENODEV;
2881 for (qfe_slot = 0; qfe_slot < 4; qfe_slot++)
2882 if (qp->happy_meals[qfe_slot] == NULL)
2883 break;
2884 if (qfe_slot == 4)
2885 return -ENODEV;
2886 }
2887
2888 dev = init_etherdev(NULL, sizeof(struct happy_meal));
2889 if (!dev)
2890 return -ENOMEM;
2891 SET_MODULE_OWNER(dev);
2892
2893 if (hme_version_printed++ == 0)
2894 printk(KERN_INFO "%s", version);
2895
2896 if (!qfe_slot) {
2897 struct pci_dev *qpdev = qp->quattro_dev;
2898
2899 prom_name[0] = 0;
2900 if (!strncmp(dev->name, "eth", 3)) {
2901 int i = simple_strtoul(dev->name + 3, NULL, 10);
2902 sprintf(prom_name, "-%d", i + 3);
2903 }
2904 printk(KERN_INFO "%s%s: Quattro HME (PCI/CheerIO) 10/100baseT Ethernet ", dev->name, prom_name);
2905 if (qpdev->vendor == PCI_VENDOR_ID_DEC &&
2906 qpdev->device == PCI_DEVICE_ID_DEC_21153)
2907 printk("DEC 21153 PCI Bridge\n");
2908 else
2909 printk("unknown bridge %04x.%04x\n",
2910 qpdev->vendor, qpdev->device);
2911 }
2912 if (qfe_slot != -1)
2913 printk(KERN_INFO "%s: Quattro HME slot %d (PCI/CheerIO) 10/100baseT Ethernet ",
2914 dev->name, qfe_slot);
2915 else
2916 printk(KERN_INFO "%s: HAPPY MEAL (PCI/CheerIO) 10/100BaseT Ethernet ",
2917 dev->name);
2918
2919 dev->base_addr = (long) pdev;
2920
2921 hp = (struct happy_meal *)dev->priv;
2922 memset(hp, 0, sizeof(*hp));
2923
2924 hp->happy_dev = pdev;
2925
2926 spin_lock_init(&hp->happy_lock);
2927
2928 if (qp != NULL) {
2929 hp->qfe_parent = qp;
2930 hp->qfe_ent = qfe_slot;
2931 qp->happy_meals[qfe_slot] = dev;
2932 }
2933
2934 hpreg_base = pci_resource_start(pdev, 0);
2935 if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0) {
2936 printk(KERN_ERR "happymeal(PCI): Cannot find proper PCI device base address.\n");
2937 return -ENODEV;
2938 }
2939 if ((hpreg_base = (unsigned long) ioremap(hpreg_base, 0x8000)) == 0) {
2940 printk(KERN_ERR "happymeal(PCI): Unable to remap card memory.\n");
2941 return -ENODEV;
2942 }
2943
2944 for (i = 0; i < 6; i++) {
2945 if (macaddr[i] != 0)
2946 break;
2947 }
2948 if (i < 6) { /* a mac address was given */
2949 for (i = 0; i < 6; i++)
2950 dev->dev_addr[i] = macaddr[i];
2951 } else {
2952 #ifdef __sparc__
2953 if (qfe_slot != -1 &&
2954 prom_getproplen(node, "local-mac-address") == 6) {
2955 prom_getproperty(node, "local-mac-address",
2956 dev->dev_addr, 6);
2957 } else {
2958 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2959 }
2960 #else
2961 memset(dev->dev_addr, 0, 6);
2962 #endif
2963 }
2964
2965 for (i = 0; i < 6; i++)
2966 printk("%2.2x%c", dev->dev_addr[i], i == 5 ? ' ' : ':');
2967
2968 printk("\n");
2969
2970 /* Layout registers. */
2971 hp->gregs = (hpreg_base + 0x0000UL);
2972 hp->etxregs = (hpreg_base + 0x2000UL);
2973 hp->erxregs = (hpreg_base + 0x4000UL);
2974 hp->bigmacregs = (hpreg_base + 0x6000UL);
2975 hp->tcvregs = (hpreg_base + 0x7000UL);
2976
2977 #ifdef __sparc__
2978 hp->hm_revision = prom_getintdefault(node, "hm-rev", 0xff);
2979 if (hp->hm_revision == 0xff)
2980 hp->hm_revision = 0xa0;
2981 #else
2982 /* works with this on non-sparc hosts */
2983 hp->hm_revision = 0x20;
2984 #endif
2985
2986 /* Now enable the feature flags we can. */
2987 if (hp->hm_revision == 0x20 || hp->hm_revision == 0x21)
2988 hp->happy_flags = HFLAG_20_21;
2989 else if (hp->hm_revision != 0xa0)
2990 hp->happy_flags = HFLAG_NOT_A0;
2991
2992 if (qp != NULL)
2993 hp->happy_flags |= HFLAG_QUATTRO;
2994
2995 /* And of course, indicate this is PCI. */
2996 hp->happy_flags |= HFLAG_PCI;
2997
2998 #ifdef __sparc__
2999 /* Assume PCI happy meals can handle all burst sizes. */
3000 hp->happy_bursts = DMA_BURSTBITS;
3001 #endif
3002
3003 hp->happy_block = (struct hmeal_init_block *)
3004 pci_alloc_consistent(pdev, PAGE_SIZE, &hp->hblock_dvma);
3005
3006 if (!hp->happy_block) {
3007 printk(KERN_ERR "happymeal(PCI): Cannot get hme init block.\n");
3008 return -ENODEV;
3009 }
3010
3011 hp->linkcheck = 0;
3012 hp->timer_state = asleep;
3013 hp->timer_ticks = 0;
3014
3015 init_timer(&hp->happy_timer);
3016
3017 hp->dev = dev;
3018 dev->open = &happy_meal_open;
3019 dev->stop = &happy_meal_close;
3020 dev->hard_start_xmit = &happy_meal_start_xmit;
3021 dev->get_stats = &happy_meal_get_stats;
3022 dev->set_multicast_list = &happy_meal_set_multicast;
3023 dev->do_ioctl = &happy_meal_ioctl;
3024 dev->irq = pdev->irq;
3025 dev->dma = 0;
3026
3027 /* Happy Meal can do it all... */
3028 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM;
3029
3030 #if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
3031 /* Hook up PCI register/dma accessors. */
3032 hp->read_desc32 = pci_hme_read_desc32;
3033 hp->write_txd = pci_hme_write_txd;
3034 hp->write_rxd = pci_hme_write_rxd;
3035 hp->dma_map = (u32 (*)(void *, void *, long, int))pci_map_single;
3036 hp->dma_unmap = (void (*)(void *, u32, long, int))pci_unmap_single;
3037 hp->dma_sync = (void (*)(void *, u32, long, int))pci_dma_sync_single;
3038 hp->read32 = pci_hme_read32;
3039 hp->write32 = pci_hme_write32;
3040 #endif
3041
3042 /* Grrr, Happy Meal comes up by default not advertising
3043 * full duplex 100baseT capabilities, fix this.
3044 */
3045 happy_meal_set_initial_advertisement(hp);
3046
3047 ether_setup(dev);
3048
3049 /* We are home free at this point, link us in to the happy
3050 * device list.
3051 */
3052 dev->ifindex = dev_new_index();
3053 hp->next_module = root_happy_dev;
3054 root_happy_dev = hp;
3055
3056 return 0;
3057 }
3058 #endif
3059
3060 #ifdef CONFIG_SBUS
3061 static int __init happy_meal_sbus_probe(void)
3062 {
3063 struct sbus_bus *sbus;
3064 struct sbus_dev *sdev;
3065 int cards = 0;
3066 char model[128];
3067
3068 for_each_sbus(sbus) {
3069 for_each_sbusdev(sdev, sbus) {
3070 char *name = sdev->prom_name;
3071
3072 if (!strcmp(name, "SUNW,hme")) {
3073 cards++;
3074 prom_getstring(sdev->prom_node, "model",
3075 model, sizeof(model));
3076 if (!strcmp(model, "SUNW,sbus-qfe"))
3077 happy_meal_sbus_init(sdev, 1);
3078 else
3079 happy_meal_sbus_init(sdev, 0);
3080 } else if (!strcmp(name, "qfe") ||
3081 !strcmp(name, "SUNW,qfe")) {
3082 cards++;
3083 happy_meal_sbus_init(sdev, 1);
3084 }
3085 }
3086 }
3087 if (cards != 0)
3088 quattro_sbus_register_irqs();
3089 return cards;
3090 }
3091 #endif
3092
3093 #ifdef CONFIG_PCI
3094 static int __init happy_meal_pci_probe(void)
3095 {
3096 struct pci_dev *pdev = NULL;
3097 int cards = 0;
3098
3099 while ((pdev = pci_find_device(PCI_VENDOR_ID_SUN,
3100 PCI_DEVICE_ID_SUN_HAPPYMEAL, pdev)) != NULL) {
3101 if (pci_enable_device(pdev))
3102 continue;
3103 cards++;
3104 happy_meal_pci_init(pdev);
3105 }
3106 return cards;
3107 }
3108 #endif
3109
3110 static int __init happy_meal_probe(void)
3111 {
3112 static int called = 0;
3113 int cards;
3114
3115 root_happy_dev = NULL;
3116
3117 if (called)
3118 return -ENODEV;
3119 called++;
3120
3121 cards = 0;
3122 #ifdef CONFIG_SBUS
3123 cards += happy_meal_sbus_probe();
3124 #endif
3125 #ifdef CONFIG_PCI
3126 cards += happy_meal_pci_probe();
3127 #endif
3128 if (!cards)
3129 return -ENODEV;
3130 return 0;
3131 }
3132
3133
3134 static void __exit happy_meal_cleanup_module(void)
3135 {
3136 #ifdef CONFIG_SBUS
3137 struct quattro *last_seen_qfe = NULL;
3138 #endif
3139
3140 while (root_happy_dev) {
3141 struct happy_meal *hp = root_happy_dev;
3142 struct happy_meal *next = root_happy_dev->next_module;
3143
3144 #ifdef CONFIG_SBUS
3145 if (!(hp->happy_flags & HFLAG_PCI)) {
3146 if (hp->happy_flags & HFLAG_QUATTRO) {
3147 if (hp->qfe_parent != last_seen_qfe) {
3148 free_irq(hp->dev->irq, hp->qfe_parent);
3149 last_seen_qfe = hp->qfe_parent;
3150 }
3151 }
3152
3153 sbus_iounmap(hp->gregs, GREG_REG_SIZE);
3154 sbus_iounmap(hp->etxregs, ETX_REG_SIZE);
3155 sbus_iounmap(hp->erxregs, ERX_REG_SIZE);
3156 sbus_iounmap(hp->bigmacregs, BMAC_REG_SIZE);
3157 sbus_iounmap(hp->tcvregs, TCVR_REG_SIZE);
3158 sbus_free_consistent(hp->happy_dev,
3159 PAGE_SIZE,
3160 hp->happy_block,
3161 hp->hblock_dvma);
3162 }
3163 #endif
3164 #ifdef CONFIG_PCI
3165 if ((hp->happy_flags & HFLAG_PCI)) {
3166 pci_free_consistent(hp->happy_dev,
3167 PAGE_SIZE,
3168 hp->happy_block,
3169 hp->hblock_dvma);
3170 iounmap((void *)hp->gregs);
3171 }
3172 #endif
3173 unregister_netdev(hp->dev);
3174 kfree(hp->dev);
3175 root_happy_dev = next;
3176 }
3177 }
3178
3179 module_init(happy_meal_probe);
3180 module_exit(happy_meal_cleanup_module);
3181
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