1 #ifndef _ACENIC_H_
2 #define _ACENIC_H_
3
4 /*
5 * Addressing:
6 *
7 * The Tigon uses 64-bit host addresses, regardless of their actual
8 * length, and it expects a big-endian format. For 32 bit systems the
9 * upper 32 bits of the address are simply ignored (zero), however for
10 * little endian 64 bit systems (Alpha) this looks strange with the
11 * two parts of the address word being swapped.
12 *
13 * The addresses are split in two 32 bit words for all architectures
14 * as some of them are in PCI shared memory and it is necessary to use
15 * readl/writel to access them.
16 *
17 * The addressing code is derived from Pete Wyckoff's work, but
18 * modified to deal properly with readl/writel usage.
19 */
20
21 struct ace_regs {
22 u32 pad0[16]; /* PCI control registers */
23
24 u32 HostCtrl; /* 0x40 */
25 u32 LocalCtrl;
26
27 u32 pad1[2];
28
29 u32 MiscCfg; /* 0x50 */
30
31 u32 pad2[2];
32
33 u32 PciState;
34
35 u32 pad3[2]; /* 0x60 */
36
37 u32 WinBase;
38 u32 WinData;
39
40 u32 pad4[12]; /* 0x70 */
41
42 u32 DmaWriteState; /* 0xa0 */
43 u32 pad5[3];
44 u32 DmaReadState; /* 0xb0 */
45
46 u32 pad6[26];
47
48 u32 AssistState;
49
50 u32 pad7[8]; /* 0x120 */
51
52 u32 CpuCtrl; /* 0x140 */
53 u32 Pc;
54
55 u32 pad8[3];
56
57 u32 SramAddr; /* 0x154 */
58 u32 SramData;
59
60 u32 pad9[49];
61
62 u32 MacRxState; /* 0x220 */
63
64 u32 pad10[7];
65
66 u32 CpuBCtrl; /* 0x240 */
67 u32 PcB;
68
69 u32 pad11[3];
70
71 u32 SramBAddr; /* 0x254 */
72 u32 SramBData;
73
74 u32 pad12[105];
75
76 u32 pad13[32]; /* 0x400 */
77 u32 Stats[32];
78
79 u32 Mb0Hi; /* 0x500 */
80 u32 Mb0Lo;
81 u32 Mb1Hi;
82 u32 CmdPrd;
83 u32 Mb2Hi;
84 u32 TxPrd;
85 u32 Mb3Hi;
86 u32 RxStdPrd;
87 u32 Mb4Hi;
88 u32 RxJumboPrd;
89 u32 Mb5Hi;
90 u32 RxMiniPrd;
91 u32 Mb6Hi;
92 u32 Mb6Lo;
93 u32 Mb7Hi;
94 u32 Mb7Lo;
95 u32 Mb8Hi;
96 u32 Mb8Lo;
97 u32 Mb9Hi;
98 u32 Mb9Lo;
99 u32 MbAHi;
100 u32 MbALo;
101 u32 MbBHi;
102 u32 MbBLo;
103 u32 MbCHi;
104 u32 MbCLo;
105 u32 MbDHi;
106 u32 MbDLo;
107 u32 MbEHi;
108 u32 MbELo;
109 u32 MbFHi;
110 u32 MbFLo;
111
112 u32 pad14[32];
113
114 u32 MacAddrHi; /* 0x600 */
115 u32 MacAddrLo;
116 u32 InfoPtrHi;
117 u32 InfoPtrLo;
118 u32 MultiCastHi; /* 0x610 */
119 u32 MultiCastLo;
120 u32 ModeStat;
121 u32 DmaReadCfg;
122 u32 DmaWriteCfg; /* 0x620 */
123 u32 TxBufRat;
124 u32 EvtCsm;
125 u32 CmdCsm;
126 u32 TuneRxCoalTicks;/* 0x630 */
127 u32 TuneTxCoalTicks;
128 u32 TuneStatTicks;
129 u32 TuneMaxTxDesc;
130 u32 TuneMaxRxDesc; /* 0x640 */
131 u32 TuneTrace;
132 u32 TuneLink;
133 u32 TuneFastLink;
134 u32 TracePtr; /* 0x650 */
135 u32 TraceStrt;
136 u32 TraceLen;
137 u32 IfIdx;
138 u32 IfMtu; /* 0x660 */
139 u32 MaskInt;
140 u32 GigLnkState;
141 u32 FastLnkState;
142 u32 pad16[4]; /* 0x670 */
143 u32 RxRetCsm; /* 0x680 */
144
145 u32 pad17[31];
146
147 u32 CmdRng[64]; /* 0x700 */
148 u32 Window[0x200];
149 };
150
151
152 typedef struct {
153 u32 addrhi;
154 u32 addrlo;
155 } aceaddr;
156
157
158 #define ACE_WINDOW_SIZE 0x800
159
160 #define ACE_JUMBO_MTU 9000
161 #define ACE_STD_MTU 1500
162
163 #define ACE_TRACE_SIZE 0x8000
164
165 /*
166 * Host control register bits.
167 */
168
169 #define IN_INT 0x01
170 #define CLR_INT 0x02
171 #define HW_RESET 0x08
172 #define BYTE_SWAP 0x10
173 #define WORD_SWAP 0x20
174 #define MASK_INTS 0x40
175
176 /*
177 * Local control register bits.
178 */
179
180 #define EEPROM_DATA_IN 0x800000
181 #define EEPROM_DATA_OUT 0x400000
182 #define EEPROM_WRITE_ENABLE 0x200000
183 #define EEPROM_CLK_OUT 0x100000
184
185 #define EEPROM_BASE 0xa0000000
186
187 #define EEPROM_WRITE_SELECT 0xa0
188 #define EEPROM_READ_SELECT 0xa1
189
190 #define SRAM_BANK_512K 0x200
191
192
193 /*
194 * udelay() values for when clocking the eeprom
195 */
196 #define ACE_SHORT_DELAY 1
197 #define ACE_LONG_DELAY 2
198
199
200 /*
201 * Misc Config bits
202 */
203
204 #define SYNC_SRAM_TIMING 0x100000
205
206
207 /*
208 * CPU state bits.
209 */
210
211 #define CPU_RESET 0x01
212 #define CPU_TRACE 0x02
213 #define CPU_PROM_FAILED 0x10
214 #define CPU_HALT 0x00010000
215 #define CPU_HALTED 0xffff0000
216
217
218 /*
219 * PCI State bits.
220 */
221
222 #define DMA_READ_MAX_4 0x04
223 #define DMA_READ_MAX_16 0x08
224 #define DMA_READ_MAX_32 0x0c
225 #define DMA_READ_MAX_64 0x10
226 #define DMA_READ_MAX_128 0x14
227 #define DMA_READ_MAX_256 0x18
228 #define DMA_READ_MAX_1K 0x1c
229 #define DMA_WRITE_MAX_4 0x20
230 #define DMA_WRITE_MAX_16 0x40
231 #define DMA_WRITE_MAX_32 0x60
232 #define DMA_WRITE_MAX_64 0x80
233 #define DMA_WRITE_MAX_128 0xa0
234 #define DMA_WRITE_MAX_256 0xc0
235 #define DMA_WRITE_MAX_1K 0xe0
236 #define DMA_READ_WRITE_MASK 0xfc
237 #define MEM_READ_MULTIPLE 0x00020000
238 #define PCI_66MHZ 0x00080000
239 #define PCI_32BIT 0x00100000
240 #define DMA_WRITE_ALL_ALIGN 0x00800000
241 #define READ_CMD_MEM 0x06000000
242 #define WRITE_CMD_MEM 0x70000000
243
244
245 /*
246 * Mode status
247 */
248
249 #define ACE_BYTE_SWAP_BD 0x02
250 #define ACE_WORD_SWAP_BD 0x04 /* not actually used */
251 #define ACE_WARN 0x08
252 #define ACE_BYTE_SWAP_DMA 0x10
253 #define ACE_NO_JUMBO_FRAG 0x200
254 #define ACE_FATAL 0x40000000
255
256
257 /*
258 * DMA config
259 */
260
261 #define DMA_THRESH_8W 0x80
262
263
264 /*
265 * Tuning parameters
266 */
267
268 #define TICKS_PER_SEC 1000000
269
270
271 /*
272 * Link bits
273 */
274
275 #define LNK_PREF 0x00008000
276 #define LNK_10MB 0x00010000
277 #define LNK_100MB 0x00020000
278 #define LNK_1000MB 0x00040000
279 #define LNK_FULL_DUPLEX 0x00080000
280 #define LNK_HALF_DUPLEX 0x00100000
281 #define LNK_TX_FLOW_CTL_Y 0x00200000
282 #define LNK_NEG_ADVANCED 0x00400000
283 #define LNK_RX_FLOW_CTL_Y 0x00800000
284 #define LNK_NIC 0x01000000
285 #define LNK_JAM 0x02000000
286 #define LNK_JUMBO 0x04000000
287 #define LNK_ALTEON 0x08000000
288 #define LNK_NEG_FCTL 0x10000000
289 #define LNK_NEGOTIATE 0x20000000
290 #define LNK_ENABLE 0x40000000
291 #define LNK_UP 0x80000000
292
293
294 /*
295 * Event definitions
296 */
297
298 #define EVT_RING_ENTRIES 256
299 #define EVT_RING_SIZE (EVT_RING_ENTRIES * sizeof(struct event))
300
301 struct event {
302 #ifdef __LITTLE_ENDIAN_BITFIELD
303 u32 idx:12;
304 u32 code:12;
305 u32 evt:8;
306 #else
307 u32 evt:8;
308 u32 code:12;
309 u32 idx:12;
310 #endif
311 u32 pad;
312 };
313
314
315 /*
316 * Events
317 */
318
319 #define E_FW_RUNNING 0x01
320 #define E_STATS_UPDATED 0x04
321
322 #define E_STATS_UPDATE 0x04
323
324 #define E_LNK_STATE 0x06
325 #define E_C_LINK_UP 0x01
326 #define E_C_LINK_DOWN 0x02
327 #define E_C_LINK_10_100 0x03
328
329 #define E_ERROR 0x07
330 #define E_C_ERR_INVAL_CMD 0x01
331 #define E_C_ERR_UNIMP_CMD 0x02
332 #define E_C_ERR_BAD_CFG 0x03
333
334 #define E_MCAST_LIST 0x08
335 #define E_C_MCAST_ADDR_ADD 0x01
336 #define E_C_MCAST_ADDR_DEL 0x02
337
338 #define E_RESET_JUMBO_RNG 0x09
339
340
341 /*
342 * Commands
343 */
344
345 #define CMD_RING_ENTRIES 64
346
347 struct cmd {
348 #ifdef __LITTLE_ENDIAN_BITFIELD
349 u32 idx:12;
350 u32 code:12;
351 u32 evt:8;
352 #else
353 u32 evt:8;
354 u32 code:12;
355 u32 idx:12;
356 #endif
357 };
358
359
360 #define C_HOST_STATE 0x01
361 #define C_C_STACK_UP 0x01
362 #define C_C_STACK_DOWN 0x02
363
364 #define C_FDR_FILTERING 0x02
365 #define C_C_FDR_FILT_ENABLE 0x01
366 #define C_C_FDR_FILT_DISABLE 0x02
367
368 #define C_SET_RX_PRD_IDX 0x03
369 #define C_UPDATE_STATS 0x04
370 #define C_RESET_JUMBO_RNG 0x05
371 #define C_ADD_MULTICAST_ADDR 0x08
372 #define C_DEL_MULTICAST_ADDR 0x09
373
374 #define C_SET_PROMISC_MODE 0x0a
375 #define C_C_PROMISC_ENABLE 0x01
376 #define C_C_PROMISC_DISABLE 0x02
377
378 #define C_LNK_NEGOTIATION 0x0b
379 #define C_C_NEGOTIATE_BOTH 0x00
380 #define C_C_NEGOTIATE_GIG 0x01
381 #define C_C_NEGOTIATE_10_100 0x02
382
383 #define C_SET_MAC_ADDR 0x0c
384 #define C_CLEAR_PROFILE 0x0d
385
386 #define C_SET_MULTICAST_MODE 0x0e
387 #define C_C_MCAST_ENABLE 0x01
388 #define C_C_MCAST_DISABLE 0x02
389
390 #define C_CLEAR_STATS 0x0f
391 #define C_SET_RX_JUMBO_PRD_IDX 0x10
392 #define C_REFRESH_STATS 0x11
393
394
395 /*
396 * Descriptor flags
397 */
398 #define BD_FLG_TCP_UDP_SUM 0x01
399 #define BD_FLG_IP_SUM 0x02
400 #define BD_FLG_END 0x04
401 #define BD_FLG_JUMBO 0x10
402 #define BD_FLG_MINI 0x1000
403
404
405 /*
406 * Ring Control block flags
407 */
408 #define RCB_FLG_TCP_UDP_SUM 0x01
409 #define RCB_FLG_IP_SUM 0x02
410 #define RCB_FLG_VLAN_ASSIST 0x10
411 #define RCB_FLG_COAL_INT_ONLY 0x20
412 #define RCB_FLG_TX_HOST_RING 0x40
413 #define RCB_FLG_IEEE_SNAP_SUM 0x80
414 #define RCB_FLG_EXT_RX_BD 0x100
415 #define RCB_FLG_RNG_DISABLE 0x200
416
417
418 /*
419 * TX ring
420 */
421 #define TX_RING_ENTRIES 256
422 #define TX_RING_SIZE (TX_RING_ENTRIES * sizeof(struct tx_desc))
423 #define TX_RING_BASE 0x3800
424
425 struct tx_desc{
426 aceaddr addr;
427 u32 flagsize;
428 #if 0
429 /*
430 * This is in PCI shared mem and must be accessed with readl/writel
431 * real layout is:
432 */
433 #if __LITTLE_ENDIAN
434 u16 flags;
435 u16 size;
436 u16 vlan;
437 u16 reserved;
438 #else
439 u16 size;
440 u16 flags;
441 u16 reserved;
442 u16 vlan;
443 #endif
444 #endif
445 u32 vlanres;
446 };
447
448
449 #define RX_STD_RING_ENTRIES 512
450 #define RX_STD_RING_SIZE (RX_STD_RING_ENTRIES * sizeof(struct rx_desc))
451
452 #define RX_JUMBO_RING_ENTRIES 256
453 #define RX_JUMBO_RING_SIZE (RX_JUMBO_RING_ENTRIES *sizeof(struct rx_desc))
454
455 #define RX_MINI_RING_ENTRIES 1024
456 #define RX_MINI_RING_SIZE (RX_MINI_RING_ENTRIES *sizeof(struct rx_desc))
457
458 #define RX_RETURN_RING_ENTRIES 2048
459 #define RX_RETURN_RING_SIZE (RX_MAX_RETURN_RING_ENTRIES * \
460 sizeof(struct rx_desc))
461
462 struct rx_desc{
463 aceaddr addr;
464 #ifdef __LITTLE_ENDIAN
465 u16 size;
466 u16 idx;
467 #else
468 u16 idx;
469 u16 size;
470 #endif
471 #ifdef __LITTLE_ENDIAN
472 u16 flags;
473 u16 type;
474 #else
475 u16 type;
476 u16 flags;
477 #endif
478 #ifdef __LITTLE_ENDIAN
479 u16 tcp_udp_csum;
480 u16 ip_csum;
481 #else
482 u16 ip_csum;
483 u16 tcp_udp_csum;
484 #endif
485 #ifdef __LITTLE_ENDIAN
486 u16 vlan;
487 u16 err_flags;
488 #else
489 u16 err_flags;
490 u16 vlan;
491 #endif
492 u32 reserved;
493 u32 opague;
494 };
495
496
497 /*
498 * This struct is shared with the NIC firmware.
499 */
500 struct ring_ctrl {
501 aceaddr rngptr;
502 #ifdef __LITTLE_ENDIAN
503 u16 flags;
504 u16 max_len;
505 #else
506 u16 max_len;
507 u16 flags;
508 #endif
509 u32 pad;
510 };
511
512
513 struct ace_mac_stats {
514 u32 excess_colls;
515 u32 coll_1;
516 u32 coll_2;
517 u32 coll_3;
518 u32 coll_4;
519 u32 coll_5;
520 u32 coll_6;
521 u32 coll_7;
522 u32 coll_8;
523 u32 coll_9;
524 u32 coll_10;
525 u32 coll_11;
526 u32 coll_12;
527 u32 coll_13;
528 u32 coll_14;
529 u32 coll_15;
530 u32 late_coll;
531 u32 defers;
532 u32 crc_err;
533 u32 underrun;
534 u32 crs_err;
535 u32 pad[3];
536 u32 drop_ula;
537 u32 drop_mc;
538 u32 drop_fc;
539 u32 drop_space;
540 u32 coll;
541 u32 kept_bc;
542 u32 kept_mc;
543 u32 kept_uc;
544 };
545
546
547 struct ace_info {
548 union {
549 u32 stats[256];
550 } s;
551 struct ring_ctrl evt_ctrl;
552 struct ring_ctrl cmd_ctrl;
553 struct ring_ctrl tx_ctrl;
554 struct ring_ctrl rx_std_ctrl;
555 struct ring_ctrl rx_jumbo_ctrl;
556 struct ring_ctrl rx_mini_ctrl;
557 struct ring_ctrl rx_return_ctrl;
558 aceaddr evt_prd_ptr;
559 aceaddr rx_ret_prd_ptr;
560 aceaddr tx_csm_ptr;
561 aceaddr stats2_ptr;
562 };
563
564
565 struct ring_info {
566 struct sk_buff *skb;
567 dma_addr_t mapping;
568 };
569
570
571 /*
572 * struct ace_skb holding the rings of skb's. This is an awful lot of
573 * pointers, but I don't see any other smart mode to do this in an
574 * efficient manner ;-(
575 */
576 struct ace_skb
577 {
578 struct ring_info tx_skbuff[TX_RING_ENTRIES];
579 struct ring_info rx_std_skbuff[RX_STD_RING_ENTRIES];
580 struct ring_info rx_mini_skbuff[RX_MINI_RING_ENTRIES];
581 struct ring_info rx_jumbo_skbuff[RX_JUMBO_RING_ENTRIES];
582 };
583
584
585 /*
586 * Struct private for the AceNIC.
587 *
588 * Elements are grouped so variables used by the tx handling goes
589 * together, and will go into the same cache lines etc. in order to
590 * avoid cache line contention between the rx and tx handling on SMP.
591 *
592 * Frequently accessed variables are put at the beginning of the
593 * struct to help the compiler generate better/shorter code.
594 */
595 struct ace_private
596 {
597 struct ace_info *info;
598 struct ace_regs *regs; /* register base */
599 struct ace_skb *skb;
600 dma_addr_t info_dma; /* 32/64 bit */
601
602 int version, link;
603 int promisc, mcast_all;
604
605 /*
606 * TX elements
607 */
608 struct tx_desc *tx_ring
609 __attribute__ ((aligned (SMP_CACHE_BYTES)));
610 struct timer_list timer; /* used by TX handling only */
611 u32 tx_prd;
612 volatile u32 tx_full, tx_ret_csm;
613
614 /*
615 * RX elements
616 */
617 unsigned long std_refill_busy
618 __attribute__ ((aligned (SMP_CACHE_BYTES)));
619 unsigned long mini_refill_busy, jumbo_refill_busy;
620 atomic_t cur_rx_bufs;
621 atomic_t cur_mini_bufs;
622 atomic_t cur_jumbo_bufs;
623 u32 rx_std_skbprd, rx_mini_skbprd, rx_jumbo_skbprd;
624 u32 cur_rx;
625
626 struct rx_desc *rx_std_ring;
627 struct rx_desc *rx_jumbo_ring;
628 struct rx_desc *rx_mini_ring;
629 struct rx_desc *rx_return_ring;
630
631 int tasklet_pending, jumbo;
632 struct tasklet_struct ace_tasklet;
633
634 struct event *evt_ring;
635
636 volatile u32 *evt_prd, *rx_ret_prd, *tx_csm;
637
638 dma_addr_t tx_ring_dma; /* 32/64 bit */
639 dma_addr_t rx_ring_base_dma;
640 dma_addr_t evt_ring_dma;
641 dma_addr_t evt_prd_dma, rx_ret_prd_dma, tx_csm_dma;
642
643 unsigned char *trace_buf;
644 struct pci_dev *pdev;
645 struct net_device *next;
646 volatile int fw_running;
647 int board_idx;
648 u16 pci_command;
649 u8 pci_latency;
650 char name[48];
651 #ifdef INDEX_DEBUG
652 spinlock_t debug_lock
653 __attribute__ ((aligned (SMP_CACHE_BYTES)));;
654 u32 last_tx, last_std_rx, last_mini_rx;
655 #endif
656 struct net_device_stats stats;
657 };
658
659
660 static inline void set_aceaddr(aceaddr *aa, dma_addr_t addr)
661 {
662 unsigned long baddr = (unsigned long) addr;
663 #ifdef ACE_64BIT_PTR
664 aa->addrlo = baddr & 0xffffffff;
665 aa->addrhi = baddr >> 32;
666 #else
667 /* Don't bother setting zero every time */
668 aa->addrlo = baddr;
669 #endif
670 mb();
671 }
672
673
674 #if 0
675 static inline void *get_aceaddr(aceaddr *aa)
676 {
677 unsigned long addr;
678 mb();
679 #ifdef ACE_64BIT_PTR
680 addr = (u64)aa->addrhi << 32 | aa->addrlo;
681 #else
682 addr = aa->addrlo;
683 #endif
684 return (void *)addr;
685 }
686 #endif
687
688
689 static inline void ace_set_txprd(struct ace_regs *regs,
690 struct ace_private *ap, u32 value)
691 {
692 #ifdef INDEX_DEBUG
693 unsigned long flags;
694 spin_lock_irqsave(&ap->debug_lock, flags);
695 writel(value, ®s->TxPrd);
696 if (value == ap->last_tx)
697 printk(KERN_ERR "AceNIC RACE ALERT! writing identical value "
698 "to tx producer (%i)\n", value);
699 ap->last_tx = value;
700 spin_unlock_irqrestore(&ap->debug_lock, flags);
701 #else
702 writel(value, ®s->TxPrd);
703 #endif
704 wmb();
705 }
706
707
708 /*
709 * Prototypes
710 */
711 static int ace_init(struct net_device *dev);
712 static void ace_load_std_rx_ring(struct ace_private *ap, int nr_bufs);
713 static void ace_load_mini_rx_ring(struct ace_private *ap, int nr_bufs);
714 static void ace_load_jumbo_rx_ring(struct ace_private *ap, int nr_bufs);
715 static void ace_interrupt(int irq, void *dev_id, struct pt_regs *regs);
716 static int ace_load_firmware(struct net_device *dev);
717 static int ace_open(struct net_device *dev);
718 static int ace_start_xmit(struct sk_buff *skb, struct net_device *dev);
719 static int ace_close(struct net_device *dev);
720 static void ace_timer(unsigned long data);
721 static void ace_tasklet(unsigned long dev);
722 static void ace_dump_trace(struct ace_private *ap);
723 static void ace_set_multicast_list(struct net_device *dev);
724 static int ace_change_mtu(struct net_device *dev, int new_mtu);
725 #ifdef SKB_RECYCLE
726 extern int ace_recycle(struct sk_buff *skb);
727 #endif
728 static int ace_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd);
729 static int ace_set_mac_addr(struct net_device *dev, void *p);
730 static void ace_set_rxtx_parms(struct net_device *dev, int jumbo);
731 static int ace_allocate_descriptors(struct net_device *dev);
732 static void ace_free_descriptors(struct net_device *dev);
733 static void ace_init_cleanup(struct net_device *dev);
734 static struct net_device_stats *ace_get_stats(struct net_device *dev);
735 static int read_eeprom_byte(struct net_device *dev, unsigned long offset);
736
737 #endif /* _ACENIC_H_ */
738
This page was automatically generated by the
LXR engine.
Visit the LXR main site for more
information.