1 /* EtherLinkXL.c: A 3Com EtherLink PCI III/XL ethernet driver for linux. */
2 /*
3 Written 1996-1999 by Donald Becker.
4
5 This software may be used and distributed according to the terms
6 of the GNU Public License, incorporated herein by reference.
7
8 This driver is for the 3Com "Vortex" and "Boomerang" series ethercards.
9 Members of the series include Fast EtherLink 3c590/3c592/3c595/3c597
10 and the EtherLink XL 3c900 and 3c905 cards.
11
12 The author may be reached as becker@scyld.com, or C/O
13 Center of Excellence in Space Data and Information Sciences
14 Code 930.5, Goddard Space Flight Center, Greenbelt MD 20771
15
16 Linux Kernel Additions:
17
18 0.99H+lk0.9 - David S. Miller - softnet, PCI DMA updates
19 0.99H+lk1.0 - Jeff Garzik <jgarzik@mandrakesoft.com>
20 Remove compatibility defines for kernel versions < 2.2.x.
21 Update for new 2.3.x module interface
22 LK1.1.2 (March 19, 2000)
23 * New PCI interface (jgarzik)
24
25 LK1.1.3 25 April 2000, Andrew Morton <andrewm@uow.edu.au>
26 - Merged with 3c575_cb.c
27 - Don't set RxComplete in boomerang interrupt enable reg
28 - spinlock in vortex_timer to protect mdio functions
29 - disable local interrupts around call to vortex_interrupt in
30 vortex_tx_timeout() (So vortex_interrupt can use spin_lock())
31 - Select window 3 in vortex_timer()'s write to Wn3_MAC_Ctrl
32 - In vortex_start_xmit(), move the lock to _after_ we've altered
33 vp->cur_tx and vp->tx_full. This defeats the race between
34 vortex_start_xmit() and vortex_interrupt which was identified
35 by Bogdan Costescu.
36 - Merged back support for six new cards from various sources
37 - Set vortex_have_pci if pci_module_init returns zero (fixes cardbus
38 insertion oops)
39 - Tell it that 3c905C has NWAY for 100bT autoneg
40 - Fix handling of SetStatusEnd in 'Too much work..' code, as
41 per 2.3.99's 3c575_cb (Dave Hinds).
42 - Split ISR into two for vortex & boomerang
43 - Fix MOD_INC/DEC races
44 - Handle resource allocation failures.
45 - Fix 3CCFE575CT LED polarity
46 - Make tx_interrupt_mitigation the default
47
48 LK1.1.4 25 April 2000, Andrew Morton <andrewm@uow.edu.au>
49 - Add extra TxReset to vortex_up() to fix 575_cb hotplug initialisation probs.
50 - Put vortex_info_tbl into __devinitdata
51 - In the vortex_error StatsFull HACK, disable stats in vp->intr_enable as well
52 as in the hardware.
53 - Increased the loop counter in wait_for_completion from 2,000 to 4,000.
54
55 LK1.1.5 28 April 2000, andrewm
56 - Added powerpc defines (John Daniel <jdaniel@etresoft.com> said these work...)
57 - Some extra diagnostics
58 - In vortex_error(), reset the Tx on maxCollisions. Otherwise most
59 chips usually get a Tx timeout.
60 - Added extra_reset module parm
61 - Replaced some inline timer manip with mod_timer
62 (Franois romieu <Francois.Romieu@nic.fr>)
63 - In vortex_up(), don't make Wn3_config initialisation dependent upon has_nway
64 (this came across from 3c575_cb).
65
66 LK1.1.6 06 Jun 2000, andrewm
67 - Backed out the PPC defines.
68 - Use del_timer_sync(), mod_timer().
69 - Fix wrapped ulong comparison in boomerang_rx()
70 - Add IS_TORNADO, use it to suppress 3c905C checksum error msg
71 (Donald Becker, I Lee Hetherington <ilh@sls.lcs.mit.edu>)
72 - Replace union wn3_config with BFINS/BFEXT manipulation for
73 sparc64 (Pete Zaitcev, Peter Jones)
74 - In vortex_error, do_tx_reset and vortex_tx_timeout(Vortex):
75 do a netif_wake_queue() to better recover from errors. (Anders Pedersen,
76 Donald Becker)
77 - Print a warning on out-of-memory (rate limited to 1 per 10 secs)
78 - Added two more Cardbus 575 NICs: 5b57 and 6564 (Paul Wagland)
79
80 LK1.1.7 2 Jul 2000 andrewm
81 - Better handling of shared IRQs
82 - Reset the transmitter on a Tx reclaim error
83 - Fixed crash under OOM during vortex_open() (Mark Hemment)
84 - Fix Rx cessation problem during OOM (help from Mark Hemment)
85 - The spinlocks around the mdio access were blocking interrupts for 300uS.
86 Fix all this to use spin_lock_bh() within mdio_read/write
87 - Only write to TxFreeThreshold if it's a boomerang - other NICs don't
88 have one.
89 - Added 802.3x MAC-layer flow control support
90
91 LK1.1.8 13 Aug 2000 andrewm
92 - Ignore request_region() return value - already reserved if Cardbus.
93 - Merged some additional Cardbus flags from Don's 0.99Qk
94 - Some fixes for 3c556 (Fred Maciel)
95 - Fix for EISA initialisation (Jan Rkorajski)
96 - Renamed MII_XCVR_PWR and EEPROM_230 to align with 3c575_cb and D. Becker's drivers
97 - Fixed MII_XCVR_PWR for 3CCFE575CT
98 - Added INVERT_LED_PWR, used it.
99 - Backed out the extra_reset stuff
100
101 LK1.1.9 12 Sep 2000 andrewm
102 - Backed out the tx_reset_resume flags. It was a no-op.
103 - In vortex_error, don't reset the Tx on txReclaim errors
104 - In vortex_error, don't reset the Tx on maxCollisions errors.
105 Hence backed out all the DownListPtr logic here.
106 - In vortex_error, give Tornado cards a partial TxReset on
107 maxCollisions (David Hinds). Defined MAX_COLLISION_RESET for this.
108 - Redid some driver flags and device names based on pcmcia_cs-3.1.20.
109 - Fixed a bug where, if vp->tx_full is set when the interface
110 is downed, it remains set when the interface is upped. Bad
111 things happen.
112
113 LK1.1.10 17 Sep 2000 andrewm
114 - Added EEPROM_8BIT for 3c555 (Fred Maciel)
115 - Added experimental support for the 3c556B Laptop Hurricane (Louis Gerbarg)
116 - Add HAS_NWAY to "3c900 Cyclone 10Mbps TPO"
117
118 LK1.1.11 13 Nov 2000 andrewm
119 - Dump MOD_INC/DEC_USE_COUNT, use SET_MODULE_OWNER
120
121 LK1.1.12 1 Jan 2001 andrewm
122 - Call pci_enable_device before we request our IRQ (Tobias Ringstrom)
123 - Add 3c590 PCI latency timer hack to vortex_probe1 (from 0.99Ra)
124 - Added extended wait_for_completion for the 3c905CX.
125 - Look for an MII on PHY index 24 first (3c905CX oddity).
126 - Add HAS_NWAY to 3cSOHO100-TX (Brett Frankenberger)
127 - Don't free skbs we don't own on oom path in vortex_open().
128
129 - See http://www.uow.edu.au/~andrewm/linux/#3c59x-2.3 for more details.
130 - Also see Documentation/networking/vortex.txt
131 */
132
133 /*
134 * FIXME: This driver _could_ support MTU changing, but doesn't. See Don's hamaci.c implementation
135 * as well as other drivers
136 *
137 * NOTE: If you make 'vortex_debug' a constant (#define vortex_debug 0) the driver shrinks by 2k
138 * due to dead code elimination. There will be some performance benefits from this due to
139 * elimination of all the tests and reduced cache footprint.
140 */
141
142 /* A few values that may be tweaked. */
143 /* Keep the ring sizes a power of two for efficiency. */
144 #define TX_RING_SIZE 16
145 #define RX_RING_SIZE 32
146 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
147
148 /* "Knobs" that adjust features and parameters. */
149 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
150 Setting to > 1512 effectively disables this feature. */
151 static const int rx_copybreak = 200;
152 /* Allow setting MTU to a larger size, bypassing the normal ethernet setup. */
153 static const int mtu = 1500;
154 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
155 static int max_interrupt_work = 32;
156 /* Tx timeout interval (millisecs) */
157 static int watchdog = 400;
158
159 /* Allow aggregation of Tx interrupts. Saves CPU load at the cost
160 * of possible Tx stalls if the system is blocking interrupts
161 * somewhere else. Undefine this to disable.
162 * AKPM 26 April 2000: enabling this still gets vestigial Tx timeouts
163 * in a heavily loaded (collision-prone) 10BaseT LAN. Should be OK with
164 * switched Ethernet.
165 * AKPM 24May00: vestigial timeouts have been removed by later fixes.
166 */
167 #define tx_interrupt_mitigation 1
168
169 /* Put out somewhat more debugging messages. (0: no msg, 1 minimal .. 6). */
170 #define vortex_debug debug
171 #ifdef VORTEX_DEBUG
172 static int vortex_debug = VORTEX_DEBUG;
173 #else
174 static int vortex_debug = 1;
175 #endif
176
177 /* Some values here only for performance evaluation and path-coverage
178 debugging. */
179 static int rx_nocopy = 0, rx_copy = 0, queued_packet = 0, rx_csumhits;
180
181 #ifndef __OPTIMIZE__
182 #error You must compile this file with the correct options!
183 #error See the last lines of the source file.
184 #error You must compile this driver with "-O".
185 #endif
186
187 #include <linux/module.h>
188 #include <linux/kernel.h>
189 #include <linux/sched.h>
190 #include <linux/string.h>
191 #include <linux/timer.h>
192 #include <linux/errno.h>
193 #include <linux/in.h>
194 #include <linux/ioport.h>
195 #include <linux/malloc.h>
196 #include <linux/interrupt.h>
197 #include <linux/pci.h>
198 #include <linux/init.h>
199 #include <linux/netdevice.h>
200 #include <linux/etherdevice.h>
201 #include <linux/skbuff.h>
202 #include <asm/irq.h> /* For NR_IRQS only. */
203 #include <asm/bitops.h>
204 #include <asm/io.h>
205
206 /* Kernel compatibility defines, some common to David Hinds' PCMCIA package.
207 This is only in the support-all-kernels source code. */
208
209 #define RUN_AT(x) (jiffies + (x))
210
211 #include <linux/delay.h>
212
213 static char version[] __devinitdata =
214 "3c59x.c:LK1.1.12 06 Jan 2000 Donald Becker and others. http://www.scyld.com/network/vortex.html " "$Revision: 1.102.2.46 $\n";
215
216 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
217 MODULE_DESCRIPTION("3Com 3c59x/3c90x/3c575 series Vortex/Boomerang/Cyclone driver");
218 MODULE_PARM(debug, "i");
219 MODULE_PARM(options, "1-" __MODULE_STRING(8) "i");
220 MODULE_PARM(full_duplex, "1-" __MODULE_STRING(8) "i");
221 MODULE_PARM(flow_ctrl, "1-" __MODULE_STRING(8) "i");
222 MODULE_PARM(rx_copybreak, "i");
223 MODULE_PARM(max_interrupt_work, "i");
224 MODULE_PARM(compaq_ioaddr, "i");
225 MODULE_PARM(compaq_irq, "i");
226 MODULE_PARM(compaq_device_id, "i");
227 MODULE_PARM(watchdog, "i");
228
229 /* Operational parameter that usually are not changed. */
230
231 /* The Vortex size is twice that of the original EtherLinkIII series: the
232 runtime register window, window 1, is now always mapped in.
233 The Boomerang size is twice as large as the Vortex -- it has additional
234 bus master control registers. */
235 #define VORTEX_TOTAL_SIZE 0x20
236 #define BOOMERANG_TOTAL_SIZE 0x40
237
238 /* Set iff a MII transceiver on any interface requires mdio preamble.
239 This only set with the original DP83840 on older 3c905 boards, so the extra
240 code size of a per-interface flag is not worthwhile. */
241 static char mii_preamble_required;
242
243 #define PFX "3c59x: "
244
245
246
247 /*
248 Theory of Operation
249
250 I. Board Compatibility
251
252 This device driver is designed for the 3Com FastEtherLink and FastEtherLink
253 XL, 3Com's PCI to 10/100baseT adapters. It also works with the 10Mbs
254 versions of the FastEtherLink cards. The supported product IDs are
255 3c590, 3c592, 3c595, 3c597, 3c900, 3c905
256
257 The related ISA 3c515 is supported with a separate driver, 3c515.c, included
258 with the kernel source or available from
259 cesdis.gsfc.nasa.gov:/pub/linux/drivers/3c515.html
260
261 II. Board-specific settings
262
263 PCI bus devices are configured by the system at boot time, so no jumpers
264 need to be set on the board. The system BIOS should be set to assign the
265 PCI INTA signal to an otherwise unused system IRQ line.
266
267 The EEPROM settings for media type and forced-full-duplex are observed.
268 The EEPROM media type should be left at the default "autoselect" unless using
269 10base2 or AUI connections which cannot be reliably detected.
270
271 III. Driver operation
272
273 The 3c59x series use an interface that's very similar to the previous 3c5x9
274 series. The primary interface is two programmed-I/O FIFOs, with an
275 alternate single-contiguous-region bus-master transfer (see next).
276
277 The 3c900 "Boomerang" series uses a full-bus-master interface with separate
278 lists of transmit and receive descriptors, similar to the AMD LANCE/PCnet,
279 DEC Tulip and Intel Speedo3. The first chip version retains a compatible
280 programmed-I/O interface that has been removed in 'B' and subsequent board
281 revisions.
282
283 One extension that is advertised in a very large font is that the adapters
284 are capable of being bus masters. On the Vortex chip this capability was
285 only for a single contiguous region making it far less useful than the full
286 bus master capability. There is a significant performance impact of taking
287 an extra interrupt or polling for the completion of each transfer, as well
288 as difficulty sharing the single transfer engine between the transmit and
289 receive threads. Using DMA transfers is a win only with large blocks or
290 with the flawed versions of the Intel Orion motherboard PCI controller.
291
292 The Boomerang chip's full-bus-master interface is useful, and has the
293 currently-unused advantages over other similar chips that queued transmit
294 packets may be reordered and receive buffer groups are associated with a
295 single frame.
296
297 With full-bus-master support, this driver uses a "RX_COPYBREAK" scheme.
298 Rather than a fixed intermediate receive buffer, this scheme allocates
299 full-sized skbuffs as receive buffers. The value RX_COPYBREAK is used as
300 the copying breakpoint: it is chosen to trade-off the memory wasted by
301 passing the full-sized skbuff to the queue layer for all frames vs. the
302 copying cost of copying a frame to a correctly-sized skbuff.
303
304 IIIC. Synchronization
305 The driver runs as two independent, single-threaded flows of control. One
306 is the send-packet routine, which enforces single-threaded use by the
307 dev->tbusy flag. The other thread is the interrupt handler, which is single
308 threaded by the hardware and other software.
309
310 IV. Notes
311
312 Thanks to Cameron Spitzer and Terry Murphy of 3Com for providing development
313 3c590, 3c595, and 3c900 boards.
314 The name "Vortex" is the internal 3Com project name for the PCI ASIC, and
315 the EISA version is called "Demon". According to Terry these names come
316 from rides at the local amusement park.
317
318 The new chips support both ethernet (1.5K) and FDDI (4.5K) packet sizes!
319 This driver only supports ethernet packets because of the skbuff allocation
320 limit of 4K.
321 */
322
323 /* This table drives the PCI probe routines. It's mostly boilerplate in all
324 of the drivers, and will likely be provided by some future kernel.
325 */
326 enum pci_flags_bit {
327 PCI_USES_IO=1, PCI_USES_MEM=2, PCI_USES_MASTER=4,
328 PCI_ADDR0=0x10<<0, PCI_ADDR1=0x10<<1, PCI_ADDR2=0x10<<2, PCI_ADDR3=0x10<<3,
329 };
330
331 enum { IS_VORTEX=1, IS_BOOMERANG=2, IS_CYCLONE=4, IS_TORNADO=8,
332 EEPROM_8BIT=0x10, /* AKPM: Uses 0x230 as the base bitmaps for EEPROM reads */
333 HAS_PWR_CTRL=0x20, HAS_MII=0x40, HAS_NWAY=0x80, HAS_CB_FNS=0x100,
334 INVERT_MII_PWR=0x200, INVERT_LED_PWR=0x400, MAX_COLLISION_RESET=0x800,
335 EEPROM_OFFSET=0x1000 };
336
337 enum vortex_chips {
338 CH_3C590 = 0,
339 CH_3C592,
340 CH_3C597,
341 CH_3C595_1,
342 CH_3C595_2,
343
344 CH_3C595_3,
345 CH_3C900_1,
346 CH_3C900_2,
347 CH_3C900_3,
348 CH_3C900_4,
349
350 CH_3C900_5,
351 CH_3C900B_FL,
352 CH_3C905_1,
353 CH_3C905_2,
354 CH_3C905B_1,
355
356 CH_3C905B_2,
357 CH_3C905B_FX,
358 CH_3C905C,
359 CH_3C980,
360 CH_3C9805,
361
362 CH_3CSOHO100_TX,
363 CH_3C555,
364 CH_3C556,
365 CH_3C556B,
366 CH_3C575,
367
368 CH_3C575_1,
369 CH_3CCFE575,
370 CH_3CCFE575CT,
371 CH_3CCFE656,
372 CH_3CCFEM656,
373
374 CH_3CCFEM656_1,
375 CH_3C450,
376 };
377
378
379 /* note: this array directly indexed by above enums, and MUST
380 * be kept in sync with both the enums above, and the PCI device
381 * table below
382 */
383 static struct vortex_chip_info {
384 const char *name;
385 int flags;
386 int drv_flags;
387 int io_size;
388 } vortex_info_tbl[] __devinitdata = {
389 #define EISA_TBL_OFFSET 0 /* Offset of this entry for vortex_eisa_init */
390 {"3c590 Vortex 10Mbps",
391 PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },
392 {"3c592 EISA 10mbps Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
393 PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },
394 {"3c597 EISA Fast Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
395 PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },
396 {"3c595 Vortex 100baseTx",
397 PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },
398 {"3c595 Vortex 100baseT4",
399 PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },
400
401 {"3c595 Vortex 100base-MII",
402 PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, },
403 {"3c900 Boomerang 10baseT",
404 PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG, 64, },
405 {"3c900 Boomerang 10Mbps Combo",
406 PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG, 64, },
407 {"3c900 Cyclone 10Mbps TPO", /* AKPM: from Don's 0.99M */
408 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY, 128, },
409 {"3c900 Cyclone 10Mbps Combo",
410 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE, 128, },
411
412 {"3c900 Cyclone 10Mbps TPC", /* AKPM: from Don's 0.99M */
413 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE, 128, },
414 {"3c900B-FL Cyclone 10base-FL",
415 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE, 128, },
416 {"3c905 Boomerang 100baseTx",
417 PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|HAS_MII, 64, },
418 {"3c905 Boomerang 100baseT4",
419 PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|HAS_MII, 64, },
420 {"3c905B Cyclone 100baseTx",
421 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY, 128, },
422
423 {"3c905B Cyclone 10/100/BNC",
424 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY, 128, },
425 {"3c905B-FX Cyclone 100baseFx",
426 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE, 128, },
427 {"3c905C Tornado",
428 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY, 128, },
429 {"3c980 Cyclone",
430 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE, 128, },
431 {"3c980 10/100 Base-TX NIC(Python-T)",
432 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE, 128, },
433
434 {"3cSOHO100-TX Hurricane",
435 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY, 128, },
436 {"3c555 Laptop Hurricane",
437 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|EEPROM_8BIT, 128, },
438 {"3c556 Laptop Tornado",
439 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_8BIT|HAS_CB_FNS|INVERT_MII_PWR, 128, },
440 {"3c556B Laptop Hurricane",
441 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_OFFSET|HAS_CB_FNS|INVERT_MII_PWR, 128, },
442 {"3c575 [Megahertz] 10/100 LAN CardBus",
443 PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
444
445 {"3c575 Boomerang CardBus",
446 PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
447 {"3CCFE575BT Cyclone CardBus",
448 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_LED_PWR, 128, },
449 {"3CCFE575CT Tornado CardBus",
450 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|MAX_COLLISION_RESET, 128, },
451 {"3CCFE656 Cyclone CardBus",
452 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|INVERT_LED_PWR, 128, },
453 {"3CCFEM656B Cyclone+Winmodem CardBus",
454 PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|INVERT_LED_PWR, 128, },
455
456 {"3CXFEM656C Tornado+Winmodem CardBus", /* From pcmcia-cs-3.1.5 */
457 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|MAX_COLLISION_RESET, 128, },
458 {"3c450 HomePNA Tornado", /* AKPM: from Don's 0.99Q */
459 PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY, 128, },
460 {0,}, /* 0 terminated list. */
461 };
462
463
464 static struct pci_device_id vortex_pci_tbl[] __devinitdata = {
465 { 0x10B7, 0x5900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C590 },
466 { 0x10B7, 0x5920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C592 },
467 { 0x10B7, 0x5970, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C597 },
468 { 0x10B7, 0x5950, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_1 },
469 { 0x10B7, 0x5951, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_2 },
470
471 { 0x10B7, 0x5952, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_3 },
472 { 0x10B7, 0x9000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_1 },
473 { 0x10B7, 0x9001, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_2 },
474 { 0x10B7, 0x9004, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_3 },
475 { 0x10B7, 0x9005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_4 },
476
477 { 0x10B7, 0x9006, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_5 },
478 { 0x10B7, 0x900A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900B_FL },
479 { 0x10B7, 0x9050, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_1 },
480 { 0x10B7, 0x9051, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_2 },
481 { 0x10B7, 0x9055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_1 },
482
483 { 0x10B7, 0x9058, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_2 },
484 { 0x10B7, 0x905A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_FX },
485 { 0x10B7, 0x9200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905C },
486 { 0x10B7, 0x9800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C980 },
487 { 0x10B7, 0x9805, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9805 },
488
489 { 0x10B7, 0x7646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CSOHO100_TX },
490 { 0x10B7, 0x5055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C555 },
491 { 0x10B7, 0x6055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556 },
492 { 0x10B7, 0x6056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556B },
493 { 0x10B7, 0x5b57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575 },
494
495 { 0x10B7, 0x5057, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575_1 },
496 { 0x10B7, 0x5157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575 },
497 { 0x10B7, 0x5257, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575CT },
498 { 0x10B7, 0x6560, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE656 },
499 { 0x10B7, 0x6562, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656 },
500
501 { 0x10B7, 0x6564, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656_1 },
502 { 0x10B7, 0x4500, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C450 },
503 {0,} /* 0 terminated list. */
504 };
505 MODULE_DEVICE_TABLE(pci, vortex_pci_tbl);
506
507
508 /* Operational definitions.
509 These are not used by other compilation units and thus are not
510 exported in a ".h" file.
511
512 First the windows. There are eight register windows, with the command
513 and status registers available in each.
514 */
515 #define EL3WINDOW(win_num) outw(SelectWindow + (win_num), ioaddr + EL3_CMD)
516 #define EL3_CMD 0x0e
517 #define EL3_STATUS 0x0e
518
519 /* The top five bits written to EL3_CMD are a command, the lower
520 11 bits are the parameter, if applicable.
521 Note that 11 parameters bits was fine for ethernet, but the new chip
522 can handle FDDI length frames (~4500 octets) and now parameters count
523 32-bit 'Dwords' rather than octets. */
524
525 enum vortex_cmd {
526 TotalReset = 0<<11, SelectWindow = 1<<11, StartCoax = 2<<11,
527 RxDisable = 3<<11, RxEnable = 4<<11, RxReset = 5<<11,
528 UpStall = 6<<11, UpUnstall = (6<<11)+1,
529 DownStall = (6<<11)+2, DownUnstall = (6<<11)+3,
530 RxDiscard = 8<<11, TxEnable = 9<<11, TxDisable = 10<<11, TxReset = 11<<11,
531 FakeIntr = 12<<11, AckIntr = 13<<11, SetIntrEnb = 14<<11,
532 SetStatusEnb = 15<<11, SetRxFilter = 16<<11, SetRxThreshold = 17<<11,
533 SetTxThreshold = 18<<11, SetTxStart = 19<<11,
534 StartDMAUp = 20<<11, StartDMADown = (20<<11)+1, StatsEnable = 21<<11,
535 StatsDisable = 22<<11, StopCoax = 23<<11, SetFilterBit = 25<<11,};
536
537 /* The SetRxFilter command accepts the following classes: */
538 enum RxFilter {
539 RxStation = 1, RxMulticast = 2, RxBroadcast = 4, RxProm = 8 };
540
541 /* Bits in the general status register. */
542 enum vortex_status {
543 IntLatch = 0x0001, HostError = 0x0002, TxComplete = 0x0004,
544 TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020,
545 IntReq = 0x0040, StatsFull = 0x0080,
546 DMADone = 1<<8, DownComplete = 1<<9, UpComplete = 1<<10,
547 DMAInProgress = 1<<11, /* DMA controller is still busy.*/
548 CmdInProgress = 1<<12, /* EL3_CMD is still busy.*/
549 };
550
551 /* Register window 1 offsets, the window used in normal operation.
552 On the Vortex this window is always mapped at offsets 0x10-0x1f. */
553 enum Window1 {
554 TX_FIFO = 0x10, RX_FIFO = 0x10, RxErrors = 0x14,
555 RxStatus = 0x18, Timer=0x1A, TxStatus = 0x1B,
556 TxFree = 0x1C, /* Remaining free bytes in Tx buffer. */
557 };
558 enum Window0 {
559 Wn0EepromCmd = 10, /* Window 0: EEPROM command register. */
560 Wn0EepromData = 12, /* Window 0: EEPROM results register. */
561 IntrStatus=0x0E, /* Valid in all windows. */
562 };
563 enum Win0_EEPROM_bits {
564 EEPROM_Read = 0x80, EEPROM_WRITE = 0x40, EEPROM_ERASE = 0xC0,
565 EEPROM_EWENB = 0x30, /* Enable erasing/writing for 10 msec. */
566 EEPROM_EWDIS = 0x00, /* Disable EWENB before 10 msec timeout. */
567 };
568 /* EEPROM locations. */
569 enum eeprom_offset {
570 PhysAddr01=0, PhysAddr23=1, PhysAddr45=2, ModelID=3,
571 EtherLink3ID=7, IFXcvrIO=8, IRQLine=9,
572 NodeAddr01=10, NodeAddr23=11, NodeAddr45=12,
573 DriverTune=13, Checksum=15};
574
575 enum Window2 { /* Window 2. */
576 Wn2_ResetOptions=12,
577 };
578 enum Window3 { /* Window 3: MAC/config bits. */
579 Wn3_Config=0, Wn3_MAC_Ctrl=6, Wn3_Options=8,
580 };
581
582 #define BFEXT(value, offset, bitcount) \
583 ((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1))
584
585 #define BFINS(lhs, rhs, offset, bitcount) \
586 (((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \
587 (((rhs) & ((1 << (bitcount)) - 1)) << (offset)))
588
589 #define RAM_SIZE(v) BFEXT(v, 0, 3)
590 #define RAM_WIDTH(v) BFEXT(v, 3, 1)
591 #define RAM_SPEED(v) BFEXT(v, 4, 2)
592 #define ROM_SIZE(v) BFEXT(v, 6, 2)
593 #define RAM_SPLIT(v) BFEXT(v, 16, 2)
594 #define XCVR(v) BFEXT(v, 20, 4)
595 #define AUTOSELECT(v) BFEXT(v, 24, 1)
596
597 enum Window4 { /* Window 4: Xcvr/media bits. */
598 Wn4_FIFODiag = 4, Wn4_NetDiag = 6, Wn4_PhysicalMgmt=8, Wn4_Media = 10,
599 };
600 enum Win4_Media_bits {
601 Media_SQE = 0x0008, /* Enable SQE error counting for AUI. */
602 Media_10TP = 0x00C0, /* Enable link beat and jabber for 10baseT. */
603 Media_Lnk = 0x0080, /* Enable just link beat for 100TX/100FX. */
604 Media_LnkBeat = 0x0800,
605 };
606 enum Window7 { /* Window 7: Bus Master control. */
607 Wn7_MasterAddr = 0, Wn7_MasterLen = 6, Wn7_MasterStatus = 12,
608 };
609 /* Boomerang bus master control registers. */
610 enum MasterCtrl {
611 PktStatus = 0x20, DownListPtr = 0x24, FragAddr = 0x28, FragLen = 0x2c,
612 TxFreeThreshold = 0x2f, UpPktStatus = 0x30, UpListPtr = 0x38,
613 };
614
615 /* The Rx and Tx descriptor lists.
616 Caution Alpha hackers: these types are 32 bits! Note also the 8 byte
617 alignment contraint on tx_ring[] and rx_ring[]. */
618 #define LAST_FRAG 0x80000000 /* Last Addr/Len pair in descriptor. */
619 #define DN_COMPLETE 0x00010000 /* This packet has been downloaded */
620 struct boom_rx_desc {
621 u32 next; /* Last entry points to 0. */
622 s32 status;
623 u32 addr; /* Up to 63 addr/len pairs possible. */
624 s32 length; /* Set LAST_FRAG to indicate last pair. */
625 };
626 /* Values for the Rx status entry. */
627 enum rx_desc_status {
628 RxDComplete=0x00008000, RxDError=0x4000,
629 /* See boomerang_rx() for actual error bits */
630 IPChksumErr=1<<25, TCPChksumErr=1<<26, UDPChksumErr=1<<27,
631 IPChksumValid=1<<29, TCPChksumValid=1<<30, UDPChksumValid=1<<31,
632 };
633
634 struct boom_tx_desc {
635 u32 next; /* Last entry points to 0. */
636 s32 status; /* bits 0:12 length, others see below. */
637 u32 addr;
638 s32 length;
639 };
640
641 /* Values for the Tx status entry. */
642 enum tx_desc_status {
643 CRCDisable=0x2000, TxDComplete=0x8000,
644 AddIPChksum=0x02000000, AddTCPChksum=0x04000000, AddUDPChksum=0x08000000,
645 TxIntrUploaded=0x80000000, /* IRQ when in FIFO, but maybe not sent. */
646 };
647
648 /* Chip features we care about in vp->capabilities, read from the EEPROM. */
649 enum ChipCaps { CapBusMaster=0x20, CapPwrMgmt=0x2000 };
650
651 struct vortex_private {
652 /* The Rx and Tx rings should be quad-word-aligned. */
653 struct boom_rx_desc* rx_ring;
654 struct boom_tx_desc* tx_ring;
655 dma_addr_t rx_ring_dma;
656 dma_addr_t tx_ring_dma;
657 /* The addresses of transmit- and receive-in-place skbuffs. */
658 struct sk_buff* rx_skbuff[RX_RING_SIZE];
659 struct sk_buff* tx_skbuff[TX_RING_SIZE];
660 struct net_device *next_module; /* NULL if PCI device */
661 unsigned int cur_rx, cur_tx; /* The next free ring entry */
662 unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */
663 struct net_device_stats stats;
664 struct sk_buff *tx_skb; /* Packet being eaten by bus master ctrl. */
665 dma_addr_t tx_skb_dma; /* Allocated DMA address for bus master ctrl DMA. */
666
667 /* PCI configuration space information. */
668 struct pci_dev *pdev;
669 char *cb_fn_base; /* CardBus function status addr space. */
670
671 /* The remainder are related to chip state, mostly media selection. */
672 struct timer_list timer; /* Media selection timer. */
673 struct timer_list rx_oom_timer; /* Rx skb allocation retry timer */
674 int options; /* User-settable misc. driver options. */
675 unsigned int media_override:4, /* Passed-in media type. */
676 default_media:4, /* Read from the EEPROM/Wn3_Config. */
677 full_duplex:1, force_fd:1, autoselect:1,
678 bus_master:1, /* Vortex can only do a fragment bus-m. */
679 full_bus_master_tx:1, full_bus_master_rx:2, /* Boomerang */
680 flow_ctrl:1, /* Use 802.3x flow control (PAUSE only) */
681 partner_flow_ctrl:1, /* Partner supports flow control */
682 tx_full:1,
683 has_nway:1,
684 open:1,
685 must_free_region:1; /* Flag: if zero, Cardbus owns the I/O region */
686 int drv_flags;
687 u16 status_enable;
688 u16 intr_enable;
689 u16 available_media; /* From Wn3_Options. */
690 u16 capabilities, info1, info2; /* Various, from EEPROM. */
691 u16 advertising; /* NWay media advertisement */
692 unsigned char phys[2]; /* MII device addresses. */
693 u16 deferred; /* Resend these interrupts when we
694 * bale from the ISR */
695 u16 io_size; /* Size of PCI region (for release_region) */
696 spinlock_t lock; /* Serialise access to device & its vortex_private */
697 spinlock_t mdio_lock; /* Serialise access to mdio hardware */
698 };
699
700 /* The action to take with a media selection timer tick.
701 Note that we deviate from the 3Com order by checking 10base2 before AUI.
702 */
703 enum xcvr_types {
704 XCVR_10baseT=0, XCVR_AUI, XCVR_10baseTOnly, XCVR_10base2, XCVR_100baseTx,
705 XCVR_100baseFx, XCVR_MII=6, XCVR_NWAY=8, XCVR_ExtMII=9, XCVR_Default=10,
706 };
707
708 static struct media_table {
709 char *name;
710 unsigned int media_bits:16, /* Bits to set in Wn4_Media register. */
711 mask:8, /* The transceiver-present bit in Wn3_Config.*/
712 next:8; /* The media type to try next. */
713 int wait; /* Time before we check media status. */
714 } media_tbl[] = {
715 { "10baseT", Media_10TP,0x08, XCVR_10base2, (14*HZ)/10},
716 { "10Mbs AUI", Media_SQE, 0x20, XCVR_Default, (1*HZ)/10},
717 { "undefined", 0, 0x80, XCVR_10baseT, 10000},
718 { "10base2", 0, 0x10, XCVR_AUI, (1*HZ)/10},
719 { "100baseTX", Media_Lnk, 0x02, XCVR_100baseFx, (14*HZ)/10},
720 { "100baseFX", Media_Lnk, 0x04, XCVR_MII, (14*HZ)/10},
721 { "MII", 0, 0x41, XCVR_10baseT, 3*HZ },
722 { "undefined", 0, 0x01, XCVR_10baseT, 10000},
723 { "Autonegotiate", 0, 0x41, XCVR_10baseT, 3*HZ},
724 { "MII-External", 0, 0x41, XCVR_10baseT, 3*HZ },
725 { "Default", 0, 0xFF, XCVR_10baseT, 10000},
726 };
727
728 static int vortex_probe1(struct pci_dev *pdev, long ioaddr, int irq,
729 int chip_idx, int card_idx);
730 static void vortex_up(struct net_device *dev);
731 static void vortex_down(struct net_device *dev);
732 static int vortex_open(struct net_device *dev);
733 static void mdio_sync(long ioaddr, int bits);
734 static int mdio_read(struct net_device *dev, int phy_id, int location);
735 static void mdio_write(struct net_device *vp, int phy_id, int location, int value);
736 static void vortex_timer(unsigned long arg);
737 static void rx_oom_timer(unsigned long arg);
738 static int vortex_start_xmit(struct sk_buff *skb, struct net_device *dev);
739 static int boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev);
740 static int vortex_rx(struct net_device *dev);
741 static int boomerang_rx(struct net_device *dev);
742 static void vortex_interrupt(int irq, void *dev_id, struct pt_regs *regs);
743 static void boomerang_interrupt(int irq, void *dev_id, struct pt_regs *regs);
744 static int vortex_close(struct net_device *dev);
745 static void dump_tx_ring(struct net_device *dev);
746 static void update_stats(long ioaddr, struct net_device *dev);
747 static struct net_device_stats *vortex_get_stats(struct net_device *dev);
748 static void set_rx_mode(struct net_device *dev);
749 static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
750 static void vortex_tx_timeout(struct net_device *dev);
751 static void acpi_set_WOL(struct net_device *dev);
752
753 /* This driver uses 'options' to pass the media type, full-duplex flag, etc. */
754 /* Option count limit only -- unlimited interfaces are supported. */
755 #define MAX_UNITS 8
756 static int options[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1,};
757 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
758 static int flow_ctrl[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
759
760 /* #define dev_alloc_skb dev_alloc_skb_debug */
761
762 /* A list of all installed Vortex EISA devices, for removing the driver module. */
763 static struct net_device *root_vortex_eisa_dev;
764
765 /* Variables to work-around the Compaq PCI BIOS32 problem. */
766 static int compaq_ioaddr, compaq_irq, compaq_device_id = 0x5900;
767
768 static int vortex_cards_found;
769
770 static void vortex_suspend (struct pci_dev *pdev)
771 {
772 struct net_device *dev = pdev->driver_data;
773
774 printk(KERN_DEBUG "vortex_suspend(%s)\n", dev->name);
775
776 if (dev && dev->priv) {
777 struct vortex_private *vp = (struct vortex_private *)dev->priv;
778 if (vp->open) {
779 netif_device_detach(dev);
780 vortex_down(dev);
781 }
782 }
783 }
784
785 static void vortex_resume (struct pci_dev *pdev)
786 {
787 struct net_device *dev = pdev->driver_data;
788
789 printk(KERN_DEBUG "vortex_resume(%s)\n", dev->name);
790
791 if (dev && dev->priv) {
792 struct vortex_private *vp = (struct vortex_private *)dev->priv;
793 if (vp->open) {
794 vortex_up(dev);
795 netif_device_attach(dev);
796 }
797 }
798 }
799
800 /* returns count found (>= 0), or negative on error */
801 static int __init vortex_eisa_init (void)
802 {
803 long ioaddr;
804 int rc;
805 int orig_cards_found = vortex_cards_found;
806
807 /* Now check all slots of the EISA bus. */
808 if (!EISA_bus)
809 return 0;
810
811 for (ioaddr = 0x1000; ioaddr < 0x9000; ioaddr += 0x1000) {
812 int device_id;
813
814 if (request_region(ioaddr, VORTEX_TOTAL_SIZE, "3c59x") == NULL)
815 continue;
816
817 /* Check the standard EISA ID register for an encoded '3Com'. */
818 if (inw(ioaddr + 0xC80) != 0x6d50) {
819 release_region (ioaddr, VORTEX_TOTAL_SIZE);
820 continue;
821 }
822
823 /* Check for a product that we support, 3c59{2,7} any rev. */
824 device_id = (inb(ioaddr + 0xC82)<<8) + inb(ioaddr + 0xC83);
825 if ((device_id & 0xFF00) != 0x5900) {
826 release_region (ioaddr, VORTEX_TOTAL_SIZE);
827 continue;
828 }
829
830 rc = vortex_probe1(NULL, ioaddr, inw(ioaddr + 0xC88) >> 12,
831 EISA_TBL_OFFSET,
832 vortex_cards_found);
833 if (rc == 0)
834 vortex_cards_found++;
835 else
836 release_region (ioaddr, VORTEX_TOTAL_SIZE);
837 }
838
839 /* Special code to work-around the Compaq PCI BIOS32 problem. */
840 if (compaq_ioaddr) {
841 vortex_probe1(NULL, compaq_ioaddr, compaq_irq,
842 compaq_device_id, vortex_cards_found++);
843 }
844
845 return vortex_cards_found - orig_cards_found;
846 }
847
848 /* returns count (>= 0), or negative on error */
849 static int __devinit vortex_init_one (struct pci_dev *pdev,
850 const struct pci_device_id *ent)
851 {
852 int rc;
853
854 /* wake up and enable device */
855 if (pci_enable_device (pdev)) {
856 rc = -EIO;
857 } else {
858 rc = vortex_probe1 (pdev, pci_resource_start (pdev, 0), pdev->irq,
859 ent->driver_data, vortex_cards_found);
860 if (rc == 0)
861 vortex_cards_found++;
862 }
863 return rc;
864 }
865
866 /*
867 * Start up the PCI device which is described by *pdev.
868 * Return 0 on success.
869 *
870 * NOTE: pdev can be NULL, for the case of an EISA driver
871 */
872 static int __devinit vortex_probe1(struct pci_dev *pdev,
873 long ioaddr, int irq,
874 int chip_idx, int card_idx)
875 {
876 struct vortex_private *vp;
877 int option;
878 unsigned int eeprom[0x40], checksum = 0; /* EEPROM contents */
879 int i, step;
880 struct net_device *dev;
881 static int printed_version;
882 int retval;
883 struct vortex_chip_info * const vci = &vortex_info_tbl[chip_idx];
884
885 if (!printed_version) {
886 printk (KERN_INFO "%s", version);
887 printk (KERN_INFO "See Documentation/networking/vortex.txt\n");
888 printed_version = 1;
889 }
890
891 dev = init_etherdev(NULL, sizeof(*vp));
892 if (!dev) {
893 printk (KERN_ERR PFX "unable to allocate etherdev, aborting\n");
894 retval = -ENOMEM;
895 goto out;
896 }
897 SET_MODULE_OWNER(dev);
898
899 printk(KERN_INFO "%s: 3Com %s %s at 0x%lx, ",
900 dev->name,
901 pdev ? "PCI" : "EISA",
902 vci->name,
903 ioaddr);
904
905 vp = dev->priv;
906 dev->base_addr = ioaddr;
907 dev->irq = irq;
908 dev->mtu = mtu;
909 vp->drv_flags = vci->drv_flags;
910 vp->has_nway = (vci->drv_flags & HAS_NWAY) ? 1 : 0;
911 vp->io_size = vci->io_size;
912
913 /* module list only for EISA devices */
914 if (pdev == NULL) {
915 vp->next_module = root_vortex_eisa_dev;
916 root_vortex_eisa_dev = dev;
917 }
918
919 /* PCI-only startup logic */
920 if (pdev) {
921 /* EISA resources already marked, so only PCI needs to do this here */
922 /* Ignore return value, because Cardbus drivers already allocate for us */
923 if (request_region(ioaddr, vci->io_size, dev->name) != NULL)
924 vp->must_free_region = 1;
925
926 /* enable bus-mastering if necessary */
927 if (vci->flags & PCI_USES_MASTER)
928 pci_set_master (pdev);
929
930 if (vci->drv_flags & IS_VORTEX) {
931 u8 pci_latency;
932 u8 new_latency = 248;
933
934 /* Check the PCI latency value. On the 3c590 series the latency timer
935 must be set to the maximum value to avoid data corruption that occurs
936 when the timer expires during a transfer. This bug exists the Vortex
937 chip only. */
938 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &pci_latency);
939 if (pci_latency < new_latency) {
940 printk(KERN_INFO "%s: Overriding PCI latency"
941 " timer (CFLT) setting of %d, new value is %d.\n",
942 dev->name, pci_latency, new_latency);
943 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, new_latency);
944 }
945 }
946 }
947
948 spin_lock_init(&vp->lock);
949 spin_lock_init(&vp->mdio_lock);
950 vp->pdev = pdev;
951
952 /* Makes sure rings are at least 16 byte aligned. */
953 vp->rx_ring = pci_alloc_consistent(pdev, sizeof(struct boom_rx_desc) * RX_RING_SIZE
954 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
955 &vp->rx_ring_dma);
956 if (vp->rx_ring == 0) {
957 retval = -ENOMEM;
958 goto free_region;
959 }
960
961 vp->tx_ring = (struct boom_tx_desc *)(vp->rx_ring + RX_RING_SIZE);
962 vp->tx_ring_dma = vp->rx_ring_dma + sizeof(struct boom_rx_desc) * RX_RING_SIZE;
963
964 /* if we are a PCI driver, we store info in pdev->driver_data
965 * instead of a module list */
966 if (pdev)
967 pdev->driver_data = dev;
968
969 /* The lower four bits are the media type. */
970 if (dev->mem_start) {
971 /*
972 * AKPM: ewww.. The 'options' param is passed in as the third arg to the
973 * LILO 'ether=' argument for non-modular use
974 */
975 option = dev->mem_start;
976 }
977 else if (card_idx < MAX_UNITS)
978 option = options[card_idx];
979 else
980 option = -1;
981
982 vp->media_override = 7;
983 if (option >= 0) {
984 vp->media_override = ((option & 7) == 2) ? 0 : option & 15;
985 vp->full_duplex = (option & 0x200) ? 1 : 0;
986 vp->bus_master = (option & 16) ? 1 : 0;
987 }
988
989 if (card_idx < MAX_UNITS) {
990 if (full_duplex[card_idx] > 0)
991 vp->full_duplex = 1;
992 if (flow_ctrl[card_idx] > 0)
993 vp->flow_ctrl = 1;
994 }
995
996 vp->force_fd = vp->full_duplex;
997 vp->options = option;
998 /* Read the station address from the EEPROM. */
999 EL3WINDOW(0);
1000 {
1001 int base;
1002
1003 if (vci->drv_flags & EEPROM_8BIT)
1004 base = 0x230;
1005 else if (vci->drv_flags & EEPROM_OFFSET)
1006 base = EEPROM_Read + 0x30;
1007 else
1008 base = EEPROM_Read;
1009
1010 for (i = 0; i < 0x40; i++) {
1011 int timer;
1012 outw(base + i, ioaddr + Wn0EepromCmd);
1013 /* Pause for at least 162 us. for the read to take place. */
1014 for (timer = 10; timer >= 0; timer--) {
1015 udelay(162);
1016 if ((inw(ioaddr + Wn0EepromCmd) & 0x8000) == 0)
1017 break;
1018 }
1019 eeprom[i] = inw(ioaddr + Wn0EepromData);
1020 }
1021 }
1022 for (i = 0; i < 0x18; i++)
1023 checksum ^= eeprom[i];
1024 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1025 if (checksum != 0x00) { /* Grrr, needless incompatible change 3Com. */
1026 while (i < 0x21)
1027 checksum ^= eeprom[i++];
1028 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1029 }
1030 if ((checksum != 0x00) && !(vci->drv_flags & IS_TORNADO))
1031 printk(" ***INVALID CHECKSUM %4.4x*** ", checksum);
1032 for (i = 0; i < 3; i++)
1033 ((u16 *)dev->dev_addr)[i] = htons(eeprom[i + 10]);
1034 for (i = 0; i < 6; i++)
1035 printk("%c%2.2x", i ? ':' : ' ', dev->dev_addr[i]);
1036 EL3WINDOW(2);
1037 for (i = 0; i < 6; i++)
1038 outb(dev->dev_addr[i], ioaddr + i);
1039
1040 #ifdef __sparc__
1041 printk(", IRQ %s\n", __irq_itoa(dev->irq));
1042 #else
1043 printk(", IRQ %d\n", dev->irq);
1044 /* Tell them about an invalid IRQ. */
1045 if (vortex_debug && (dev->irq <= 0 || dev->irq >= NR_IRQS))
1046 printk(KERN_WARNING " *** Warning: IRQ %d is unlikely to work! ***\n",
1047 dev->irq);
1048 #endif
1049
1050 EL3WINDOW(4);
1051 step = (inb(ioaddr + Wn4_NetDiag) & 0x1e) >> 1;
1052 printk(KERN_INFO " product code '%c%c' rev %02x.%d date %02d-"
1053 "%02d-%02d\n", eeprom[6]&0xff, eeprom[6]>>8, eeprom[0x14],
1054 step, (eeprom[4]>>5) & 15, eeprom[4] & 31, eeprom[4]>>9);
1055
1056
1057 if (pdev && vci->drv_flags & HAS_CB_FNS) {
1058 unsigned long fn_st_addr; /* Cardbus function status space */
1059 unsigned short n;
1060
1061 fn_st_addr = pci_resource_start (pdev, 2);
1062 if (fn_st_addr)
1063 vp->cb_fn_base = ioremap(fn_st_addr, 128);
1064 printk(KERN_INFO "%s: CardBus functions mapped %8.8lx->%p\n",
1065 dev->name, fn_st_addr, vp->cb_fn_base);
1066 EL3WINDOW(2);
1067
1068 n = inw(ioaddr + Wn2_ResetOptions) & ~0x4010;
1069 if (vp->drv_flags & INVERT_LED_PWR)
1070 n |= 0x10;
1071 if (vp->drv_flags & INVERT_MII_PWR)
1072 n |= 0x4000;
1073 outw(n, ioaddr + Wn2_ResetOptions);
1074 }
1075
1076 /* Extract our information from the EEPROM data. */
1077 vp->info1 = eeprom[13];
1078 vp->info2 = eeprom[15];
1079 vp->capabilities = eeprom[16];
1080
1081 if (vp->info1 & 0x8000) {
1082 vp->full_duplex = 1;
1083 printk(KERN_INFO "Full duplex capable\n");
1084 }
1085
1086 {
1087 static const char * ram_split[] = {"5:3", "3:1", "1:1", "3:5"};
1088 unsigned int config;
1089 EL3WINDOW(3);
1090 vp->available_media = inw(ioaddr + Wn3_Options);
1091 if ((vp->available_media & 0xff) == 0) /* Broken 3c916 */
1092 vp->available_media = 0x40;
1093 config = inl(ioaddr + Wn3_Config);
1094 if (vortex_debug > 1)
1095 printk(KERN_DEBUG " Internal config register is %4.4x, "
1096 "transceivers %#x.\n", config, inw(ioaddr + Wn3_Options));
1097 printk(KERN_INFO " %dK %s-wide RAM %s Rx:Tx split, %s%s interface.\n",
1098 8 << RAM_SIZE(config),
1099 RAM_WIDTH(config) ? "word" : "byte",
1100 ram_split[RAM_SPLIT(config)],
1101 AUTOSELECT(config) ? "autoselect/" : "",
1102 XCVR(config) > XCVR_ExtMII ? "<invalid transceiver>" :
1103 media_tbl[XCVR(config)].name);
1104 vp->default_media = XCVR(config);
1105 vp->autoselect = AUTOSELECT(config);
1106 }
1107
1108 if (vp->media_override != 7) {
1109 printk(KERN_INFO " Media override to transceiver type %d (%s).\n",
1110 vp->media_override, media_tbl[vp->media_override].name);
1111 dev->if_port = vp->media_override;
1112 } else
1113 dev->if_port = vp->default_media;
1114
1115 if (dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1116 int phy, phy_idx = 0;
1117 EL3WINDOW(4);
1118 mii_preamble_required++;
1119 mii_preamble_required++;
1120 mdio_read(dev, 24, 1);
1121 for (phy = 0; phy < 32 && phy_idx < 1; phy++) {
1122 int mii_status, phyx;
1123
1124 /*
1125 * For the 3c905CX we look at index 24 first, because it bogusly
1126 * reports an external PHY at all indices
1127 */
1128 if (phy == 0)
1129 phyx = 24;
1130 else if (phy <= 24)
1131 phyx = phy - 1;
1132 else
1133 phyx = phy;
1134 mii_status = mdio_read(dev, phyx, 1);
1135 if (mii_status && mii_status != 0xffff) {
1136 vp->phys[phy_idx++] = phyx;
1137 printk(KERN_INFO " MII transceiver found at address %d,"
1138 " status %4x.\n", phyx, mii_status);
1139 if ((mii_status & 0x0040) == 0)
1140 mii_preamble_required++;
1141 }
1142 }
1143 mii_preamble_required--;
1144 if (phy_idx == 0) {
1145 printk(KERN_WARNING" ***WARNING*** No MII transceivers found!\n");
1146 vp->phys[0] = 24;
1147 } else {
1148 vp->advertising = mdio_read(dev, vp->phys[0], 4);
1149 if (vp->full_duplex) {
1150 /* Only advertise the FD media types. */
1151 vp->advertising &= ~0x02A0;
1152 mdio_write(dev, vp->phys[0], 4, vp->advertising);
1153 }
1154 }
1155 }
1156
1157 if (vp->capabilities & CapPwrMgmt)
1158 acpi_set_WOL(dev);
1159
1160 if (vp->capabilities & CapBusMaster) {
1161 vp->full_bus_master_tx = 1;
1162 printk(KERN_INFO" Enabling bus-master transmits and %s receives.\n",
1163 (vp->info2 & 1) ? "early" : "whole-frame" );
1164 vp->full_bus_master_rx = (vp->info2 & 1) ? 1 : 2;
1165 vp->bus_master = 0; /* AKPM: vortex only */
1166 }
1167
1168 /* The 3c59x-specific entries in the device structure. */
1169 dev->open = vortex_open;
1170 dev->hard_start_xmit = vp->full_bus_master_tx ?
1171 boomerang_start_xmit : vortex_start_xmit;
1172 dev->stop = vortex_close;
1173 dev->get_stats = vortex_get_stats;
1174 dev->do_ioctl = vortex_ioctl;
1175 dev->set_multicast_list = set_rx_mode;
1176 dev->tx_timeout = vortex_tx_timeout;
1177 dev->watchdog_timeo = (watchdog * HZ) / 1000;
1178 // publish_netdev(dev);
1179 return 0;
1180
1181 free_region:
1182 if (vp->must_free_region)
1183 release_region(ioaddr, vci->io_size);
1184 // withdraw_netdev(dev);
1185 unregister_netdev(dev);
1186 kfree (dev);
1187 printk(KERN_ERR PFX "vortex_probe1 fails. Returns %d\n", retval);
1188 out:
1189 return retval;
1190 }
1191
1192 static void wait_for_completion(struct net_device *dev, int cmd)
1193 {
1194 int i;
1195
1196 outw(cmd, dev->base_addr + EL3_CMD);
1197 for (i = 0; i < 2000; i++) {
1198 if (!(inw(dev->base_addr + EL3_STATUS) & CmdInProgress))
1199 return;
1200 }
1201
1202 /* OK, that didn't work. Do it the slow way. One second */
1203 for (i = 0; i < 100000; i++) {
1204 if (!(inw(dev->base_addr + EL3_STATUS) & CmdInProgress)) {
1205 printk(KERN_INFO "%s: command 0x%04x took %d usecs! Please tell andrewm@uow.edu.au\n",
1206 dev->name, cmd, i * 10);
1207 return;
1208 }
1209 udelay(10);
1210 }
1211 printk(KERN_ERR "%s: command 0x%04x did not complete! Status=0x%x\n",
1212 dev->name, cmd, inw(dev->base_addr + EL3_STATUS));
1213 }
1214
1215 static void
1216 vortex_up(struct net_device *dev)
1217 {
1218 long ioaddr = dev->base_addr;
1219 struct vortex_private *vp = (struct vortex_private *)dev->priv;
1220 unsigned int config;
1221 int i, device_id;
1222
1223 if (vp->pdev)
1224 device_id = vp->pdev->device;
1225 else
1226 device_id = 0x5900; /* EISA */
1227
1228 /* Before initializing select the active media port. */
1229 EL3WINDOW(3);
1230 config = inl(ioaddr + Wn3_Config);
1231
1232 if (vp->media_override != 7) {
1233 if (vortex_debug > 1)
1234 printk(KERN_INFO "%s: Media override to transceiver %d (%s).\n",
1235 dev->name, vp->media_override,
1236 media_tbl[vp->media_override].name);
1237 dev->if_port = vp->media_override;
1238 } else if (vp->autoselect) {
1239 if (vp->has_nway) {
1240 printk(KERN_INFO "%s: using NWAY autonegotiation\n", dev->name);
1241 dev->if_port = XCVR_NWAY;
1242 } else {
1243 /* Find first available media type, starting with 100baseTx. */
1244 dev->if_port = XCVR_100baseTx;
1245 while (! (vp->available_media & media_tbl[dev->if_port].mask))
1246 dev->if_port = media_tbl[dev->if_port].next;
1247 printk(KERN_INFO "%s: first available media type: %s\n",
1248 dev->name,
1249 media_tbl[dev->if_port].name);
1250 }
1251 } else {
1252 dev->if_port = vp->default_media;
1253 printk(KERN_INFO "%s: using default media %s\n",
1254 dev->name, media_tbl[dev->if_port].name);
1255 }
1256
1257 init_timer(&vp->timer);
1258 vp->timer.expires = RUN_AT(media_tbl[dev->if_port].wait);
1259 vp->timer.data = (unsigned long)dev;
1260 vp->timer.function = vortex_timer; /* timer handler */
1261 add_timer(&vp->timer);
1262
1263 init_timer(&vp->rx_oom_timer);
1264 vp->rx_oom_timer.data = (unsigned long)dev;
1265 vp->rx_oom_timer.function = rx_oom_timer;
1266
1267 if (vortex_debug > 1)
1268 printk(KERN_DEBUG "%s: Initial media type %s.\n",
1269 dev->name, media_tbl[dev->if_port].name);
1270
1271 vp->full_duplex = vp->force_fd;
1272 config = BFINS(config, dev->if_port, 20, 4);
1273 //AKPM if (!vp->has_nway)
1274 {
1275 if (vortex_debug > 6)
1276 printk(KERN_DEBUG "vortex_up(): writing 0x%x to InternalConfig\n",
1277 config);
1278 outl(config, ioaddr + Wn3_Config);
1279 }
1280
1281 if (dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1282 int mii_reg1, mii_reg5;
1283 EL3WINDOW(4);
1284 /* Read BMSR (reg1) only to clear old status. */
1285 mii_reg1 = mdio_read(dev, vp->phys[0], 1);
1286 mii_reg5 = mdio_read(dev, vp->phys[0], 5);
1287 if (mii_reg5 == 0xffff || mii_reg5 == 0x0000)
1288 ; /* No MII device or no link partner report */
1289 else if ((mii_reg5 & 0x0100) != 0 /* 100baseTx-FD */
1290 || (mii_reg5 & 0x00C0) == 0x0040) /* 10T-FD, but not 100-HD */
1291 vp->full_duplex = 1;
1292 vp->partner_flow_ctrl = ((mii_reg5 & 0x0400) != 0);
1293 if (vortex_debug > 1)
1294 printk(KERN_INFO "%s: MII #%d status %4.4x, link partner capability %4.4x,"
1295 " setting %s-duplex.\n", dev->name, vp->phys[0],
1296 mii_reg1, mii_reg5, vp->full_duplex ? "full" : "half");
1297 EL3WINDOW(3);
1298 }
1299
1300 /* Set the full-duplex bit. */
1301 outw( ((vp->info1 & 0x8000) || vp->full_duplex ? 0x20 : 0) |
1302 (dev->mtu > 1500 ? 0x40 : 0) |
1303 ((vp->full_duplex && vp->flow_ctrl && vp->partner_flow_ctrl) ? 0x100 : 0),
1304 ioaddr + Wn3_MAC_Ctrl);
1305
1306 if (vortex_debug > 1) {
1307 printk(KERN_DEBUG "%s: vortex_up() InternalConfig %8.8x.\n",
1308 dev->name, config);
1309 }
1310
1311 wait_for_completion(dev, TxReset);
1312 wait_for_completion(dev, RxReset);
1313
1314 outw(SetStatusEnb | 0x00, ioaddr + EL3_CMD);
1315
1316 if (vortex_debug > 1) {
1317 EL3WINDOW(4);
1318 printk(KERN_DEBUG "%s: vortex_up() irq %d media status %4.4x.\n",
1319 dev->name, dev->irq, inw(ioaddr + Wn4_Media));
1320 }
1321
1322 /* Set the station address and mask in window 2 each time opened. */
1323 EL3WINDOW(2);
1324 for (i = 0; i < 6; i++)
1325 outb(dev->dev_addr[i], ioaddr + i);
1326 for (; i < 12; i+=2)
1327 outw(0, ioaddr + i);
1328
1329 if (vp->cb_fn_base) {
1330 unsigned short n = inw(ioaddr + Wn2_ResetOptions) & ~0x4010;
1331 if (vp->drv_flags & INVERT_LED_PWR)
1332 n |= 0x10;
1333 if (vp->drv_flags & INVERT_MII_PWR)
1334 n |= 0x4000;
1335 outw(n, ioaddr + Wn2_ResetOptions);
1336 }
1337
1338 if (dev->if_port == XCVR_10base2)
1339 /* Start the thinnet transceiver. We should really wait 50ms...*/
1340 outw(StartCoax, ioaddr + EL3_CMD);
1341 if (dev->if_port != XCVR_NWAY) {
1342 EL3WINDOW(4);
1343 outw((inw(ioaddr + Wn4_Media) & ~(Media_10TP|Media_SQE)) |
1344 media_tbl[dev->if_port].media_bits, ioaddr + Wn4_Media);
1345 }
1346
1347 /* Switch to the stats window, and clear all stats by reading. */
1348 outw(StatsDisable, ioaddr + EL3_CMD);
1349 EL3WINDOW(6);
1350 for (i = 0; i < 10; i++)
1351 inb(ioaddr + i);
1352 inw(ioaddr + 10);
1353 inw(ioaddr + 12);
1354 /* New: On the Vortex we must also clear the BadSSD counter. */
1355 EL3WINDOW(4);
1356 inb(ioaddr + 12);
1357 /* ..and on the Boomerang we enable the extra statistics bits. */
1358 outw(0x0040, ioaddr + Wn4_NetDiag);
1359
1360 /* Switch to register set 7 for normal use. */
1361 EL3WINDOW(7);
1362
1363 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1364 vp->cur_rx = vp->dirty_rx = 0;
1365 /* Initialize the RxEarly register as recommended. */
1366 outw(SetRxThreshold + (1536>>2), ioaddr + EL3_CMD);
1367 outl(0x0020, ioaddr + PktStatus);
1368 outl(vp->rx_ring_dma, ioaddr + UpListPtr);
1369 }
1370 if (vp->full_bus_master_tx) { /* Boomerang bus master Tx. */
1371 vp->cur_tx = vp->dirty_tx = 0;
1372 if (vp->drv_flags & IS_BOOMERANG)
1373 outb(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold); /* Room for a packet. */
1374 /* Clear the Rx, Tx rings. */
1375 for (i = 0; i < RX_RING_SIZE; i++) /* AKPM: this is done in vortex_open, too */
1376 vp->rx_ring[i].status = 0;
1377 for (i = 0; i < TX_RING_SIZE; i++)
1378 vp->tx_skbuff[i] = 0;
1379 outl(0, ioaddr + DownListPtr);
1380 }
1381 /* Set receiver mode: presumably accept b-case and phys addr only. */
1382 set_rx_mode(dev);
1383 outw(StatsEnable, ioaddr + EL3_CMD); /* Turn on statistics. */
1384
1385 // wait_for_completion(dev, SetTxStart|0x07ff);
1386 outw(RxEnable, ioaddr + EL3_CMD); /* Enable the receiver. */
1387 outw(TxEnable, ioaddr + EL3_CMD); /* Enable transmitter. */
1388 /* Allow status bits to be seen. */
1389 vp->status_enable = SetStatusEnb | HostError|IntReq|StatsFull|TxComplete|
1390 (vp->full_bus_master_tx ? DownComplete : TxAvailable) |
1391 (vp->full_bus_master_rx ? UpComplete : RxComplete) |
1392 (vp->bus_master ? DMADone : 0);
1393 vp->intr_enable = SetIntrEnb | IntLatch | TxAvailable |
1394 (vp->full_bus_master_rx ? 0 : RxComplete) |
1395 StatsFull | HostError | TxComplete | IntReq
1396 | (vp->bus_master ? DMADone : 0) | UpComplete | DownComplete;
1397 outw(vp->status_enable, ioaddr + EL3_CMD);
1398 /* Ack all pending events, and set active indicator mask. */
1399 outw(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,
1400 ioaddr + EL3_CMD);
1401 outw(vp->intr_enable, ioaddr + EL3_CMD);
1402 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
1403 writel(0x8000, vp->cb_fn_base + 4);
1404 netif_start_queue (dev);
1405 }
1406
1407 static int
1408 vortex_open(struct net_device *dev)
1409 {
1410 struct vortex_private *vp = (struct vortex_private *)dev->priv;
1411 int i;
1412 int retval;
1413
1414 /* Use the now-standard shared IRQ implementation. */
1415 if ((retval = request_irq(dev->irq, vp->full_bus_master_rx ?
1416 &boomerang_interrupt : &vortex_interrupt, SA_SHIRQ, dev->name, dev))) {
1417 printk(KERN_ERR "%s: Could not reserve IRQ %d\n", dev->name, dev->irq);
1418 goto out;
1419 }
1420
1421 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1422 if (vortex_debug > 2)
1423 printk(KERN_DEBUG "%s: Filling in the Rx ring.\n", dev->name);
1424 for (i = 0; i < RX_RING_SIZE; i++) {
1425 struct sk_buff *skb;
1426 vp->rx_ring[i].next = cpu_to_le32(vp->rx_ring_dma + sizeof(struct boom_rx_desc) * (i+1));
1427 vp->rx_ring[i].status = 0; /* Clear complete bit. */
1428 vp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ | LAST_FRAG);
1429 skb = dev_alloc_skb(PKT_BUF_SZ);
1430 vp->rx_skbuff[i] = skb;
1431 if (skb == NULL)
1432 break; /* Bad news! */
1433 skb->dev = dev; /* Mark as being used by this device. */
1434 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
1435 vp->rx_ring[i].addr = cpu_to_le32(pci_map_single(vp->pdev, skb->tail, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
1436 }
1437 if (i != RX_RING_SIZE) {
1438 int j;
1439 printk(KERN_EMERG "%s: no memory for rx ring\n", dev->name);
1440 for (j = 0; j < i; j++) {
1441 if (vp->rx_skbuff[j]) {
1442 dev_kfree_skb(vp->rx_skbuff[j]);
1443 vp->rx_skbuff[j] = 0;
1444 }
1445 }
1446 retval = -ENOMEM;
1447 goto out_free_irq;
1448 }
1449 /* Wrap the ring. */
1450 vp->rx_ring[i-1].next = cpu_to_le32(vp->rx_ring_dma);
1451 }
1452
1453 vortex_up(dev);
1454 vp->open = 1;
1455 vp->tx_full = 0;
1456 return 0;
1457
1458 out_free_irq:
1459 free_irq(dev->irq, dev);
1460 out:
1461 if (vortex_debug > 1)
1462 printk(KERN_ERR "%s: vortex_open() fails: returning %d\n", dev->name, retval);
1463 return retval;
1464 }
1465
1466 static void vortex_timer(unsigned long data)
1467 {
1468 struct net_device *dev = (struct net_device *)data;
1469 struct vortex_private *vp = (struct vortex_private *)dev->priv;
1470 long ioaddr = dev->base_addr;
1471 int next_tick = 60*HZ;
1472 int ok = 0;
1473 int media_status, mii_status, old_window;
1474
1475 if (vortex_debug > 2) {
1476 printk(KERN_DEBUG "%s: Media selection timer tick happened, %s.\n",
1477 dev->name, media_tbl[dev->if_port].name);
1478 printk(KERN_DEBUG "dev->watchdog_timeo=%d\n", dev->watchdog_timeo);
1479 }
1480
1481 disable_irq(dev->irq);
1482 old_window = inw(ioaddr + EL3_CMD) >> 13;
1483 EL3WINDOW(4);
1484 media_status = inw(ioaddr + Wn4_Media);
1485 switch (dev->if_port) {
1486 case XCVR_10baseT: case XCVR_100baseTx: case XCVR_100baseFx:
1487 if (media_status & Media_LnkBeat) {
1488 ok = 1;
1489 if (vortex_debug > 1)
1490 printk(KERN_DEBUG "%s: Media %s has link beat, %x.\n",
1491 dev->name, media_tbl[dev->if_port].name, media_status);
1492 } else if (vortex_debug > 1)
1493 printk(KERN_DEBUG "%s: Media %s has no link beat, %x.\n",
1494 dev->name, media_tbl[dev->if_port].name, media_status);
1495 break;
1496 case XCVR_MII: case XCVR_NWAY:
1497 {
1498 mii_status = mdio_read(dev, vp->phys[0], 1);
1499 ok = 1;
1500 if (vortex_debug > 2)
1501 printk(KERN_DEBUG "%s: MII transceiver has status %4.4x.\n",
1502 dev->name, mii_status);
1503 if (mii_status & 0x0004) {
1504 int mii_reg5 = mdio_read(dev, vp->phys[0], 5);
1505 if (! vp->force_fd && mii_reg5 != 0xffff) {
1506 int duplex = (mii_reg5&0x0100) ||
1507 (mii_reg5 & 0x01C0) == 0x0040;
1508 if (vp->full_duplex != duplex) {
1509 vp->full_duplex = duplex;
1510 printk(KERN_INFO "%s: Setting %s-duplex based on MII "
1511 "#%d link partner capability of %4.4x.\n",
1512 dev->name, vp->full_duplex ? "full" : "half",
1513 vp->phys[0], mii_reg5);
1514 /* Set the full-duplex bit. */
1515 EL3WINDOW(3); /* AKPM: this was missing from 2.3.99 3c59x.c! */
1516 outw( (vp->full_duplex ? 0x20 : 0) |
1517 (dev->mtu > 1500 ? 0x40 : 0) |
1518 ((vp->full_duplex && vp->flow_ctrl && vp->partner_flow_ctrl) ? 0x100 : 0),
1519 ioaddr + Wn3_MAC_Ctrl);
1520 if (vortex_debug > 1)
1521 printk(KERN_DEBUG "Setting duplex in Wn3_MAC_Ctrl\n");
1522 /* AKPM: bug: should reset Tx and Rx after setting Duplex. Page 180 */
1523 }
1524 }
1525 }
1526 }
1527 break;
1528 default: /* Other media types handled by Tx timeouts. */
1529 if (vortex_debug > 1)
1530 printk(KERN_DEBUG "%s: Media %s has no indication, %x.\n",
1531 dev->name, media_tbl[dev->if_port].name, media_status);
1532 ok = 1;
1533 }
1534 if ( ! ok) {
1535 unsigned int config;
1536
1537 do {
1538 dev->if_port = media_tbl[dev->if_port].next;
1539 } while ( ! (vp->available_media & media_tbl[dev->if_port].mask));
1540 if (dev->if_port == XCVR_Default) { /* Go back to default. */
1541 dev->if_port = vp->default_media;
1542 if (vortex_debug > 1)
1543 printk(KERN_DEBUG "%s: Media selection failing, using default "
1544 "%s port.\n",
1545 dev->name, media_tbl[dev->if_port].name);
1546 } else {
1547 if (vortex_debug > 1)
1548 printk(KERN_DEBUG "%s: Media selection failed, now trying "
1549 "%s port.\n",
1550 dev->name, media_tbl[dev->if_port].name);
1551 next_tick = media_tbl[dev->if_port].wait;
1552 }
1553 outw((media_status & ~(Media_10TP|Media_SQE)) |
1554 media_tbl[dev->if_port].media_bits, ioaddr + Wn4_Media);
1555
1556 EL3WINDOW(3);
1557 config = inl(ioaddr + Wn3_Config);
1558 config = BFINS(config, dev->if_port, 20, 4);
1559 outl(config, ioaddr + Wn3_Config);
1560
1561 outw(dev->if_port == XCVR_10base2 ? StartCoax : StopCoax,
1562 ioaddr + EL3_CMD);
1563 if (vortex_debug > 1)
1564 printk(KERN_DEBUG "wrote 0x%08x to Wn3_Config\n", config);
1565 /* AKPM: FIXME: Should reset Rx & Tx here. P60 of 3c90xc.pdf */
1566 }
1567 EL3WINDOW(old_window);
1568 enable_irq(dev->irq);
1569
1570 if (vortex_debug > 2)
1571 printk(KERN_DEBUG "%s: Media selection timer finished, %s.\n",
1572 dev->name, media_tbl[dev->if_port].name);
1573
1574 mod_timer(&vp->timer, RUN_AT(next_tick));
1575 if (vp->deferred)
1576 outw(FakeIntr, ioaddr + EL3_CMD);
1577 return;
1578 }
1579
1580 static void vortex_tx_timeout(struct net_device *dev)
1581 {
1582 struct vortex_private *vp = (struct vortex_private *)dev->priv;
1583 long ioaddr = dev->base_addr;
1584
1585 printk(KERN_ERR "%s: transmit timed out, tx_status %2.2x status %4.4x.\n",
1586 dev->name, inb(ioaddr + TxStatus),
1587 inw(ioaddr + EL3_STATUS));
1588 EL3WINDOW(4);
1589 printk(KERN_ERR " diagnostics: net %04x media %04x dma %8.8x.\n",
1590 inw(ioaddr + Wn4_NetDiag), inw(ioaddr + Wn4_Media),
1591 inl(ioaddr + PktStatus));
1592 /* Slight code bloat to be user friendly. */
1593 if ((inb(ioaddr + TxStatus) & 0x88) == 0x88)
1594 printk(KERN_ERR "%s: Transmitter encountered 16 collisions --"
1595 " network cable problem?\n", dev->name);
1596 if (inw(ioaddr + EL3_STATUS) & IntLatch) {
1597 printk(KERN_ERR "%s: Interrupt posted but not delivered --"
1598 " IRQ blocked by another device?\n", dev->name);
1599 /* Bad idea here.. but we might as well handle a few events. */
1600 {
1601 /*
1602 * AKPM: block interrupts because vortex_interrupt
1603 * does a bare spin_lock()
1604 */
1605 unsigned long flags;
1606 local_irq_save(flags);
1607 if (vp->full_bus_master_tx)
1608 boomerang_interrupt(dev->irq, dev, 0);
1609 else
1610 vortex_interrupt(dev->irq, dev, 0);
1611 local_irq_restore(flags);
1612 }
1613 }
1614
1615 if (vortex_debug > 0)
1616 dump_tx_ring(dev);
1617
1618 wait_for_completion(dev, TxReset);
1619
1620 vp->stats.tx_errors++;
1621 if (vp->full_bus_master_tx) {
1622 if (vortex_debug > 0)
1623 printk(KERN_DEBUG "%s: Resetting the Tx ring pointer.\n",
1624 dev->name);
1625 if (vp->cur_tx - vp->dirty_tx > 0 && inl(ioaddr + DownListPtr) == 0)
1626 outl(vp->tx_ring_dma + (vp->dirty_tx % TX_RING_SIZE) * sizeof(struct boom_tx_desc),
1627 ioaddr + DownListPtr);
1628 if (vp->tx_full && (vp->cur_tx - vp->dirty_tx <= TX_RING_SIZE - 1)) {
1629 vp->tx_full = 0;
1630 netif_wake_queue (dev);
1631 }
1632 if (vp->tx_full)
1633 netif_stop_queue (dev);
1634 if (vp->drv_flags & IS_BOOMERANG)
1635 outb(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold);
1636 outw(DownUnstall, ioaddr + EL3_CMD);
1637 } else {
1638 vp->stats.tx_dropped++;
1639 netif_wake_queue(dev);
1640 }
1641
1642 /* Issue Tx Enable */
1643 outw(TxEnable, ioaddr + EL3_CMD);
1644 dev->trans_start = jiffies;
1645
1646 /* Switch to register set 7 for normal use. */
1647 EL3WINDOW(7);
1648 }
1649
1650 /*
1651 * Handle uncommon interrupt sources. This is a separate routine to minimize
1652 * the cache impact.
1653 */
1654 static void
1655 vortex_error(struct net_device *dev, int status)
1656 {
1657 struct vortex_private *vp = (struct vortex_private *)dev->priv;
1658 long ioaddr = dev->base_addr;
1659 int do_tx_reset = 0, reset_mask = 0;
1660 unsigned char tx_status = 0;
1661
1662 if (vortex_debug > 2) {
1663 printk(KERN_DEBUG "%s: vortex_error(), status=0x%x\n", dev->name, status);
1664 }
1665
1666 if (status & TxComplete) { /* Really "TxError" for us. */
1667 tx_status = inb(ioaddr + TxStatus);
1668 /* Presumably a tx-timeout. We must merely re-enable. */
1669 if (vortex_debug > 2
1670 || (tx_status != 0x88 && vortex_debug > 0)) {
1671 printk(KERN_DEBUG"%s: Transmit error, Tx status register %2.2x.\n",
1672 dev->name, tx_status);
1673 dump_tx_ring(dev);
1674 }
1675 if (tx_status & 0x14) vp->stats.tx_fifo_errors++;
1676 if (tx_status & 0x38) vp->stats.tx_aborted_errors++;
1677 outb(0, ioaddr + TxStatus);
1678 if (tx_status & 0x30) { /* txJabber or txUnderrun */
1679 do_tx_reset = 1;
1680 } else if ((tx_status & 0x08) && (vp->drv_flags & MAX_COLLISION_RESET)) { /* maxCollisions */
1681 do_tx_reset = 1;
1682 reset_mask = 0x0108; /* Reset interface logic, but not download logic */
1683 } else { /* Merely re-enable the transmitter. */
1684 outw(TxEnable, ioaddr + EL3_CMD);
1685 }
1686 }
1687
1688 if (status & RxEarly) { /* Rx early is unused. */
1689 vortex_rx(dev);
1690 outw(AckIntr | RxEarly, ioaddr + EL3_CMD);
1691 }
1692 if (status & StatsFull) { /* Empty statistics. */
1693 static int DoneDidThat;
1694 if (vortex_debug > 4)
1695 printk(KERN_DEBUG "%s: Updating stats.\n", dev->name);
1696 update_stats(ioaddr, dev);
1697 /* HACK: Disable statistics as an interrupt source. */
1698 /* This occurs when we have the wrong media type! */
1699 if (DoneDidThat == 0 &&
1700 inw(ioaddr + EL3_STATUS) & StatsFull) {
1701 printk(KERN_WARNING "%s: Updating statistics failed, disabling "
1702 "stats as an interrupt source.\n", dev->name);
1703 EL3WINDOW(5);
1704 outw(SetIntrEnb | (inw(ioaddr + 10) & ~StatsFull), ioaddr + EL3_CMD);
1705 vp->intr_enable &= ~StatsFull;
1706 EL3WINDOW(7);
1707 DoneDidThat++;
1708 }
1709 }
1710 if (status & IntReq) { /* Restore all interrupt sources. */
1711 outw(vp->status_enable, ioaddr + EL3_CMD);
1712 outw(vp->intr_enable, ioaddr + EL3_CMD);
1713 }
1714 if (status & HostError) {
1715 u16 fifo_diag;
1716 EL3WINDOW(4);
1717 fifo_diag = inw(ioaddr + Wn4_FIFODiag);
1718 printk(KERN_ERR "%s: Host error, FIFO diagnostic register %4.4x.\n",
1719 dev->name, fifo_diag);
1720 /* Adapter failure requires Tx/Rx reset and reinit. */
1721 if (vp->full_bus_master_tx) {
1722 int bus_status = inl(ioaddr + PktStatus);
1723 /* 0x80000000 PCI master abort. */
1724 /* 0x40000000 PCI target abort. */
1725 if (vortex_debug)
1726 printk(KERN_ERR "%s: PCI bus error, bus status %8.8x\n", dev->name, bus_status);
1727
1728 /* In this case, blow the card away */
1729 vortex_down(dev);
1730 wait_for_completion(dev, TotalReset | 0xff);
1731 vortex_up(dev); /* AKPM: bug. vortex_up() assumes that the rx ring is full. It may not be. */
1732 } else if (fifo_diag & 0x0400)
1733 do_tx_reset = 1;
1734 if (fifo_diag & 0x3000) {
1735 wait_for_completion(dev, RxReset);
1736 /* Set the Rx filter to the current state. */
1737 set_rx_mode(dev);
1738 outw(RxEnable, ioaddr + EL3_CMD); /* Re-enable the receiver. */
1739 outw(AckIntr | HostError, ioaddr + EL3_CMD);
1740 }
1741 }
1742
1743 if (do_tx_reset) {
1744 wait_for_completion(dev, TxReset|reset_mask);
1745 outw(TxEnable, ioaddr + EL3_CMD);
1746 if (!vp->full_bus_master_tx)
1747 netif_wake_queue(dev);
1748 }
1749 }
1750
1751 static int
1752 vortex_start_xmit(struct sk_buff *skb, struct net_device *dev)
1753 {
1754 struct vortex_private *vp = (struct vortex_private *)dev->priv;
1755 long ioaddr = dev->base_addr;
1756
1757 /* Put out the doubleword header... */
1758 outl(skb->len, ioaddr + TX_FIFO);
1759 if (vp->bus_master) {
1760 /* Set the bus-master controller to transfer the packet. */
1761 int len = (skb->len + 3) & ~3;
1762 outl( vp->tx_skb_dma = pci_map_single(vp->pdev, skb->data, len, PCI_DMA_TODEVICE),
1763 ioaddr + Wn7_MasterAddr);
1764 outw(len, ioaddr + Wn7_MasterLen);
1765 vp->tx_skb = skb;
1766 outw(StartDMADown, ioaddr + EL3_CMD);
1767 /* netif_wake_queue() will be called at the DMADone interrupt. */
1768 } else {
1769 /* ... and the packet rounded to a doubleword. */
1770 outsl(ioaddr + TX_FIFO, skb->data, (skb->len + 3) >> 2);
1771 dev_kfree_skb (skb);
1772 if (inw(ioaddr + TxFree) > 1536) {
1773 netif_start_queue (dev); /* AKPM: redundant? */
1774 } else {
1775 /* Interrupt us when the FIFO has room for max-sized packet. */
1776 netif_stop_queue(dev);
1777 outw(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
1778 }
1779 }
1780
1781 dev->trans_start = jiffies;
1782
1783 /* Clear the Tx status stack. */
1784 {
1785 int tx_status;
1786 int i = 32;
1787
1788 while (--i > 0 && (tx_status = inb(ioaddr + TxStatus)) > 0) {
1789 if (tx_status & 0x3C) { /* A Tx-disabling error occurred. */
1790 if (vortex_debug > 2)
1791 printk(KERN_DEBUG "%s: Tx error, status %2.2x.\n",
1792 dev->name, tx_status);
1793 if (tx_status & 0x04) vp->stats.tx_fifo_errors++;
1794 if (tx_status & 0x38) vp->stats.tx_aborted_errors++;
1795 if (tx_status & 0x30) {
1796 wait_for_completion(dev, TxReset);
1797 }
1798 outw(TxEnable, ioaddr + EL3_CMD);
1799 }
1800 outb(0x00, ioaddr + TxStatus); /* Pop the status stack. */
1801 }
1802 }
1803 return 0;
1804 }
1805
1806 static int
1807 boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev)
1808 {
1809 struct vortex_private *vp = (struct vortex_private *)dev->priv;
1810 long ioaddr = dev->base_addr;
1811 /* Calculate the next Tx descriptor entry. */
1812 int entry = vp->cur_tx % TX_RING_SIZE;
1813 struct boom_tx_desc *prev_entry = &vp->tx_ring[(vp->cur_tx-1) % TX_RING_SIZE];
1814 unsigned long flags;
1815
1816 if (vortex_debug > 6) {
1817 printk(KERN_DEBUG "boomerang_start_xmit()\n");
1818 if (vortex_debug > 3)
1819 printk(KERN_DEBUG "%s: Trying to send a packet, Tx index %d.\n",
1820 dev->name, vp->cur_tx);
1821 }
1822
1823 if (vp->tx_full) {
1824 if (vortex_debug > 0)
1825 printk(KERN_WARNING "%s: Tx Ring full, refusing to send buffer.\n",
1826 dev->name);
1827 return 1;
1828 }
1829 vp->tx_skbuff[entry] = skb;
1830 vp->tx_ring[entry].next = 0;
1831 vp->tx_ring[entry].addr = cpu_to_le32(pci_map_single(vp->pdev, skb->data, skb->len, PCI_DMA_TODEVICE));
1832 vp->tx_ring[entry].length = cpu_to_le32(skb->len | LAST_FRAG);
1833 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
1834
1835 spin_lock_irqsave(&vp->lock, flags);
1836 /* Wait for the stall to complete. */
1837 wait_for_completion(dev, DownStall);
1838 prev_entry->next = cpu_to_le32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc));
1839 if (inl(ioaddr + DownListPtr) == 0) {
1840 outl(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc), ioaddr + DownListPtr);
1841 queued_packet++;
1842 }
1843
1844 vp->cur_tx++;
1845 if (vp->cur_tx - vp->dirty_tx > TX_RING_SIZE - 1) {
1846 vp->tx_full = 1;
1847 netif_stop_queue (dev);
1848 } else { /* Clear previous interrupt enable. */
1849 #if defined(tx_interrupt_mitigation)
1850 prev_entry->status &= cpu_to_le32(~TxIntrUploaded);
1851 #endif
1852 /* netif_start_queue (dev); */ /* AKPM: redundant? */
1853 }
1854 outw(DownUnstall, ioaddr + EL3_CMD);
1855 spin_unlock_irqrestore(&vp->lock, flags);
1856 dev->trans_start = jiffies;
1857 return 0;
1858 }
1859
1860 /* The interrupt handler does all of the Rx thread work and cleans up
1861 after the Tx thread. */
1862
1863 /*
1864 * This is the ISR for the vortex series chips.
1865 * full_bus_master_tx == 0 && full_bus_master_rx == 0
1866 */
1867
1868 static void vortex_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1869 {
1870 struct net_device *dev = dev_id;
1871 struct vortex_private *vp = (struct vortex_private *)dev->priv;
1872 long ioaddr;
1873 int status;
1874 int work_done = max_interrupt_work;
1875
1876 ioaddr = dev->base_addr;
1877 spin_lock(&vp->lock);
1878
1879 status = inw(ioaddr + EL3_STATUS);
1880
1881 if (vortex_debug > 6)
1882 printk("vortex_interrupt(). status=0x%4x\n", status);
1883
1884 if ((status & IntLatch) == 0)
1885 goto handler_exit; /* No interrupt: shared IRQs cause this */
1886
1887 if (status & IntReq) {
1888 status |= vp->deferred;
1889 vp->deferred = 0;
1890 }
1891
1892 if (status == 0xffff) /* AKPM: h/w no longer present (hotplug)? */
1893 goto handler_exit;
1894
1895 if (vortex_debug > 4)
1896 printk(KERN_DEBUG "%s: interrupt, status %4.4x, latency %d ticks.\n",
1897 dev->name, status, inb(ioaddr + Timer));
1898
1899 do {
1900 if (vortex_debug > 5)
1901 printk(KERN_DEBUG "%s: In interrupt loop, status %4.4x.\n",
1902 dev->name, status);
1903 if (status & RxComplete)
1904 vortex_rx(dev);
1905
1906 if (status & TxAvailable) {
1907 if (vortex_debug > 5)
1908 printk(KERN_DEBUG " TX room bit was handled.\n");
1909 /* There's room in the FIFO for a full-sized packet. */
1910 outw(AckIntr | TxAvailable, ioaddr + EL3_CMD);
1911 netif_wake_queue (dev);
1912 }
1913
1914 if (status & DMADone) {
1915 if (inw(ioaddr + Wn7_MasterStatus) & 0x1000) {
1916 outw(0x1000, ioaddr + Wn7_MasterStatus); /* Ack the event. */
1917 pci_unmap_single(vp->pdev, vp->tx_skb_dma, (vp->tx_skb->len + 3) & ~3, PCI_DMA_TODEVICE);
1918 dev_kfree_skb_irq(vp->tx_skb); /* Release the transferred buffer */
1919 if (inw(ioaddr + TxFree) > 1536) {
1920 /*
1921 * AKPM: FIXME: I don't think we need this. If the queue was stopped due to
1922 * insufficient FIFO room, the TxAvailable test will succeed and call
1923 * netif_wake_queue()
1924 */
1925 netif_wake_queue(dev);
1926 } else { /* Interrupt when FIFO has room for max-sized packet. */
1927 outw(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
1928 netif_stop_queue(dev); /* AKPM: This is new */
1929 }
1930 }
1931 }
1932 /* Check for all uncommon interrupts at once. */
1933 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq)) {
1934 if (status == 0xffff)
1935 break;
1936 vortex_error(dev, status);
1937 }
1938
1939 if (--work_done < 0) {
1940 printk(KERN_WARNING "%s: Too much work in interrupt, status "
1941 "%4.4x.\n", dev->name, status);
1942 /* Disable all pending interrupts. */
1943 do {
1944 vp->deferred |= status;
1945 outw(SetStatusEnb | (~vp->deferred & vp->status_enable),
1946 ioaddr + EL3_CMD);
1947 outw(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
1948 } while ((status = inw(ioaddr + EL3_CMD)) & IntLatch);
1949 /* The timer will reenable interrupts. */
1950 mod_timer(&vp->timer, jiffies + 1*HZ);
1951 break;
1952 }
1953 /* Acknowledge the IRQ. */
1954 outw(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
1955 } while ((status = inw(ioaddr + EL3_STATUS)) & (IntLatch | RxComplete));
1956
1957 if (vortex_debug > 4)
1958 printk(KERN_DEBUG "%s: exiting interrupt, status %4.4x.\n",
1959 dev->name, status);
1960 handler_exit:
1961 spin_unlock(&vp->lock);
1962 }
1963
1964 /*
1965 * This is the ISR for the boomerang series chips.
1966 * full_bus_master_tx == 1 && full_bus_master_rx == 1
1967 */
1968
1969 static void boomerang_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1970 {
1971 struct net_device *dev = dev_id;
1972 struct vortex_private *vp = (struct vortex_private *)dev->priv;
1973 long ioaddr;
1974 int status;
1975 int work_done = max_interrupt_work;
1976
1977 ioaddr = dev->base_addr;
1978
1979 /*
1980 * It seems dopey to put the spinlock this early, but we could race against vortex_tx_timeout
1981 * and boomerang_start_xmit
1982 */
1983 spin_lock(&vp->lock);
1984
1985 status = inw(ioaddr + EL3_STATUS);
1986
1987 if (vortex_debug > 6)
1988 printk(KERN_DEBUG "boomerang_interrupt. status=0x%4x\n", status);
1989
1990 if ((status & IntLatch) == 0)
1991 goto handler_exit; /* No interrupt: shared IRQs can cause this */
1992
1993 if (status == 0xffff) { /* AKPM: h/w no longer present (hotplug)? */
1994 if (vortex_debug > 1)
1995 printk(KERN_DEBUG "boomerang_interrupt(1): status = 0xffff\n");
1996 goto handler_exit;
1997 }
1998
1999 if (status & IntReq) {
2000 status |= vp->deferred;
2001 vp->deferred = 0;
2002 }
2003
2004 if (vortex_debug > 4)
2005 printk(KERN_DEBUG "%s: interrupt, status %4.4x, latency %d ticks.\n",
2006 dev->name, status, inb(ioaddr + Timer));
2007 do {
2008 if (vortex_debug > 5)
2009 printk(KERN_DEBUG "%s: In interrupt loop, status %4.4x.\n",
2010 dev->name, status);
2011 if (status & UpComplete) {
2012 outw(AckIntr | UpComplete, ioaddr + EL3_CMD);
2013 if (vortex_debug > 5)
2014 printk(KERN_DEBUG "boomerang_interrupt->boomerang_rx\n");
2015 boomerang_rx(dev);
2016 }
2017
2018 if (status & DownComplete) {
2019 unsigned int dirty_tx = vp->dirty_tx;
2020
2021 outw(AckIntr | DownComplete, ioaddr + EL3_CMD);
2022 while (vp->cur_tx - dirty_tx > 0) {
2023 int entry = dirty_tx % TX_RING_SIZE;
2024 #if 1 /* AKPM: the latter is faster, but cyclone-only */
2025 if (inl(ioaddr + DownListPtr) ==
2026 vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc))
2027 break; /* It still hasn't been processed. */
2028 #else
2029 if ((vp->tx_ring[entry].status & DN_COMPLETE) == 0)
2030 break; /* It still hasn't been processed. */
2031 #endif
2032
2033 if (vp->tx_skbuff[entry]) {
2034 struct sk_buff *skb = vp->tx_skbuff[entry];
2035
2036 pci_unmap_single(vp->pdev,
2037 le32_to_cpu(vp->tx_ring[entry].addr), skb->len, PCI_DMA_TODEVICE);
2038 dev_kfree_skb_irq(skb);
2039 vp->tx_skbuff[entry] = 0;
2040 } else {
2041 printk(KERN_DEBUG "boomerang_interrupt: no skb!\n");
2042 }
2043 /* vp->stats.tx_packets++; Counted below. */
2044 dirty_tx++;
2045 }
2046 vp->dirty_tx = dirty_tx;
2047 if (vp->tx_full && (vp->cur_tx - dirty_tx <= TX_RING_SIZE - 1)) {
2048 if (vortex_debug > 6)
2049 printk(KERN_DEBUG "boomerang_interrupt: clearing tx_full\n");
2050 vp->tx_full = 0;
2051 netif_wake_queue (dev);
2052 }
2053 }
2054
2055 /* Check for all uncommon interrupts at once. */
2056 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq))
2057 vortex_error(dev, status);
2058
2059 if (--work_done < 0) {
2060 printk(KERN_WARNING "%s: Too much work in interrupt, status "
2061 "%4.4x.\n", dev->name, status);
2062 /* Disable all pending interrupts. */
2063 do {
2064 vp->deferred |= status;
2065 outw(SetStatusEnb | (~vp->deferred & vp->status_enable),
2066 ioaddr + EL3_CMD);
2067 outw(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2068 } while ((status = inw(ioaddr + EL3_CMD)) & IntLatch);
2069 /* The timer will reenable interrupts. */
2070 mod_timer(&vp->timer, jiffies + 1*HZ);
2071 break;
2072 }
2073 /* Acknowledge the IRQ. */
2074 outw(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2075 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
2076 writel(0x8000, vp->cb_fn_base + 4);
2077
2078 } while ((status = inw(ioaddr + EL3_STATUS)) & IntLatch);
2079
2080 if (vortex_debug > 4)
2081 printk(KERN_DEBUG "%s: exiting interrupt, status %4.4x.\n",
2082 dev->name, status);
2083 handler_exit:
2084 spin_unlock(&vp->lock);
2085 }
2086
2087 static int vortex_rx(struct net_device *dev)
2088 {
2089 struct vortex_private *vp = (struct vortex_private *)dev->priv;
2090 long ioaddr = dev->base_addr;
2091 int i;
2092 short rx_status;
2093
2094 if (vortex_debug > 5)
2095 printk(KERN_DEBUG "vortex_rx(): status %4.4x, rx_status %4.4x.\n",
2096 inw(ioaddr+EL3_STATUS), inw(ioaddr+RxStatus));
2097 while ((rx_status = inw(ioaddr + RxStatus)) > 0) {
2098 if (rx_status & 0x4000) { /* Error, update stats. */
2099 unsigned char rx_error = inb(ioaddr + RxErrors);
2100 if (vortex_debug > 2)
2101 printk(KERN_DEBUG " Rx error: status %2.2x.\n", rx_error);
2102 vp->stats.rx_errors++;
2103 if (rx_error & 0x01) vp->stats.rx_over_errors++;
2104 if (rx_error & 0x02) vp->stats.rx_length_errors++;
2105 if (rx_error & 0x04) vp->stats.rx_frame_errors++;
2106 if (rx_error & 0x08) vp->stats.rx_crc_errors++;
2107 if (rx_error & 0x10) vp->stats.rx_length_errors++;
2108 } else {
2109 /* The packet length: up to 4.5K!. */
2110 int pkt_len = rx_status & 0x1fff;
2111 struct sk_buff *skb;
2112
2113 skb = dev_alloc_skb(pkt_len + 5);
2114 if (vortex_debug > 4)
2115 printk(KERN_DEBUG "Receiving packet size %d status %4.4x.\n",
2116 pkt_len, rx_status);
2117 if (skb != NULL) {
2118 skb->dev = dev;
2119 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2120 /* 'skb_put()' points to the start of sk_buff data area. */
2121 if (vp->bus_master &&
2122 ! (inw(ioaddr + Wn7_MasterStatus) & 0x8000)) {
2123 dma_addr_t dma = pci_map_single(vp->pdev, skb_put(skb, pkt_len),
2124 pkt_len, PCI_DMA_FROMDEVICE);
2125 outl(dma, ioaddr + Wn7_MasterAddr);
2126 outw((skb->len + 3) & ~3, ioaddr + Wn7_MasterLen);
2127 outw(StartDMAUp, ioaddr + EL3_CMD);
2128 while (inw(ioaddr + Wn7_MasterStatus) & 0x8000)
2129 ;
2130 pci_unmap_single(vp->pdev, dma, pkt_len, PCI_DMA_FROMDEVICE);
2131 } else {
2132 insl(ioaddr + RX_FIFO, skb_put(skb, pkt_len),
2133 (pkt_len + 3) >> 2);
2134 }
2135 outw(RxDiscard, ioaddr + EL3_CMD); /* Pop top Rx packet. */
2136 skb->protocol = eth_type_trans(skb, dev);
2137 netif_rx(skb);
2138 dev->last_rx = jiffies;
2139 vp->stats.rx_packets++;
2140 /* Wait a limited time to go to next packet. */
2141 for (i = 200; i >= 0; i--)
2142 if ( ! (inw(ioaddr + EL3_STATUS) & CmdInProgress))
2143 break;
2144 continue;
2145 } else if (vortex_debug > 0)
2146 printk(KERN_NOTICE "%s: No memory to allocate a sk_buff of "
2147 "size %d.\n", dev->name, pkt_len);
2148 }
2149 vp->stats.rx_dropped++;
2150 wait_for_completion(dev, RxDiscard);
2151 }
2152
2153 return 0;
2154 }
2155
2156 static int
2157 boomerang_rx(struct net_device *dev)
2158 {
2159 struct vortex_private *vp = (struct vortex_private *)dev->priv;
2160 int entry = vp->cur_rx % RX_RING_SIZE;
2161 long ioaddr = dev->base_addr;
2162 int rx_status;
2163 int rx_work_limit = vp->dirty_rx + RX_RING_SIZE - vp->cur_rx;
2164
2165 if (vortex_debug > 5)
2166 printk(KERN_DEBUG "boomerang_rx(): status %4.4x\n", inw(ioaddr+EL3_STATUS));
2167
2168 while ((rx_status = le32_to_cpu(vp->rx_ring[entry].status)) & RxDComplete){
2169 if (--rx_work_limit < 0)
2170 break;
2171 if (rx_status & RxDError) { /* Error, update stats. */
2172 unsigned char rx_error = rx_status >> 16;
2173 if (vortex_debug > 2)
2174 printk(KERN_DEBUG " Rx error: status %2.2x.\n", rx_error);
2175 vp->stats.rx_errors++;
2176 if (rx_error & 0x01) vp->stats.rx_over_errors++;
2177 if (rx_error & 0x02) vp->stats.rx_length_errors++;
2178 if (rx_error & 0x04) vp->stats.rx_frame_errors++;
2179 if (rx_error & 0x08) vp->stats.rx_crc_errors++;
2180 if (rx_error & 0x10) vp->stats.rx_length_errors++;
2181 } else {
2182 /* The packet length: up to 4.5K!. */
2183 int pkt_len = rx_status & 0x1fff;
2184 struct sk_buff *skb;
2185 dma_addr_t dma = le32_to_cpu(vp->rx_ring[entry].addr);
2186
2187 vp->stats.rx_bytes += pkt_len;
2188 if (vortex_debug > 4)
2189 printk(KERN_DEBUG "Receiving packet size %d status %4.4x.\n",
2190 pkt_len, rx_status);
2191
2192 /* Check if the packet is long enough to just accept without
2193 copying to a properly sized skbuff. */
2194 if (pkt_len < rx_copybreak && (skb = dev_alloc_skb(pkt_len + 2)) != 0) {
2195 skb->dev = dev;
2196 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2197 pci_dma_sync_single(vp->pdev, dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2198 /* 'skb_put()' points to the start of sk_buff data area. */
2199 memcpy(skb_put(skb, pkt_len),
2200 vp->rx_skbuff[entry]->tail,
2201 pkt_len);
2202 rx_copy++;
2203 } else {
2204 /* Pass up the skbuff already on the Rx ring. */
2205 skb = vp->rx_skbuff[entry];
2206 vp->rx_skbuff[entry] = NULL;
2207 skb_put(skb, pkt_len);
2208 pci_unmap_single(vp->pdev, dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2209 rx_nocopy++;
2210 }
2211 skb->protocol = eth_type_trans(skb, dev);
2212 { /* Use hardware checksum info. */
2213 int csum_bits = rx_status & 0xee000000;
2214 if (csum_bits &&
2215 (csum_bits == (IPChksumValid | TCPChksumValid) ||
2216 csum_bits == (IPChksumValid | UDPChksumValid))) {
2217 skb->ip_summed = CHECKSUM_UNNECESSARY;
2218 rx_csumhits++;
2219 }
2220 }
2221 netif_rx(skb);
2222 dev->last_rx = jiffies;
2223 vp->stats.rx_packets++;
2224 }
2225 entry = (++vp->cur_rx) % RX_RING_SIZE;
2226 }
2227 /* Refill the Rx ring buffers. */
2228 for (; vp->cur_rx - vp->dirty_rx > 0; vp->dirty_rx++) {
2229 struct sk_buff *skb;
2230 entry = vp->dirty_rx % RX_RING_SIZE;
2231 if (vp->rx_skbuff[entry] == NULL) {
2232 skb = dev_alloc_skb(PKT_BUF_SZ);
2233 if (skb == NULL) {
2234 static unsigned long last_jif;
2235 if ((jiffies - last_jif) > 10 * HZ) {
2236 printk(KERN_WARNING "%s: memory shortage\n", dev->name);
2237 last_jif = jiffies;
2238 }
2239 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE)
2240 mod_timer(&vp->rx_oom_timer, RUN_AT(HZ * 1));
2241 break; /* Bad news! */
2242 }
2243 skb->dev = dev; /* Mark as being used by this device. */
2244 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2245 vp->rx_ring[entry].addr = cpu_to_le32(pci_map_single(vp->pdev, skb->tail, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
2246 vp->rx_skbuff[entry] = skb;
2247 }
2248 vp->rx_ring[entry].status = 0; /* Clear complete bit. */
2249 outw(UpUnstall, ioaddr + EL3_CMD);
2250 }
2251 return 0;
2252 }
2253
2254 /*
2255 * If we've hit a total OOM refilling the Rx ring we poll once a second
2256 * for some memory. Otherwise there is no way to restart the rx process.
2257 */
2258 static void
2259 rx_oom_timer(unsigned long arg)
2260 {
2261 struct net_device *dev = (struct net_device *)arg;
2262 struct vortex_private *vp = (struct vortex_private *)dev->priv;
2263
2264 spin_lock_irq(&vp->lock);
2265 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE) /* This test is redundant, but makes me feel good */
2266 boomerang_rx(dev);
2267 if (vortex_debug > 1) {
2268 printk(KERN_DEBUG "%s: rx_oom_timer %s\n", dev->name,
2269 ((vp->cur_rx - vp->dirty_rx) != RX_RING_SIZE) ? "succeeded" : "retrying");
2270 }
2271 spin_unlock_irq(&vp->lock);
2272 }
2273
2274 static void
2275 vortex_down(struct net_device *dev)
2276 {
2277 struct vortex_private *vp = (struct vortex_private *)dev->priv;
2278 long ioaddr = dev->base_addr;
2279
2280 netif_stop_queue (dev);
2281
2282 del_timer_sync(&vp->rx_oom_timer);
2283 del_timer_sync(&vp->timer);
2284
2285 /* Turn off statistics ASAP. We update vp->stats below. */
2286 outw(StatsDisable, ioaddr + EL3_CMD);
2287
2288 /* Disable the receiver and transmitter. */
2289 outw(RxDisable, ioaddr + EL3_CMD);
2290 outw(TxDisable, ioaddr + EL3_CMD);
2291
2292 if (dev->if_port == XCVR_10base2)
2293 /* Turn off thinnet power. Green! */
2294 outw(StopCoax, ioaddr + EL3_CMD);
2295
2296 outw(SetIntrEnb | 0x0000, ioaddr + EL3_CMD);
2297
2298 update_stats(ioaddr, dev);
2299 if (vp->full_bus_master_rx)
2300 outl(0, ioaddr + UpListPtr);
2301 if (vp->full_bus_master_tx)
2302 outl(0, ioaddr + DownListPtr);
2303
2304 if (vp->capabilities & CapPwrMgmt)
2305 acpi_set_WOL(dev);
2306 }
2307
2308 static int
2309 vortex_close(struct net_device *dev)
2310 {
2311 struct vortex_private *vp = (struct vortex_private *)dev->priv;
2312 long ioaddr = dev->base_addr;
2313 int i;
2314
2315 if (netif_device_present(dev))
2316 vortex_down(dev);
2317
2318 if (vortex_debug > 1) {
2319 printk(KERN_DEBUG"%s: vortex_close() status %4.4x, Tx status %2.2x.\n",
2320 dev->name, inw(ioaddr + EL3_STATUS), inb(ioaddr + TxStatus));
2321 printk(KERN_DEBUG "%s: vortex close stats: rx_nocopy %d rx_copy %d"
2322 " tx_queued %d Rx pre-checksummed %d.\n",
2323 dev->name, rx_nocopy, rx_copy, queued_packet, rx_csumhits);
2324 }
2325
2326 free_irq(dev->irq, dev);
2327
2328 if (vp->full_bus_master_rx) { /* Free Boomerang bus master Rx buffers. */
2329 for (i = 0; i < RX_RING_SIZE; i++)
2330 if (vp->rx_skbuff[i]) {
2331 pci_unmap_single( vp->pdev, le32_to_cpu(vp->rx_ring[i].addr),
2332 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2333 dev_kfree_skb(vp->rx_skbuff[i]);
2334 vp->rx_skbuff[i] = 0;
2335 }
2336 }
2337 if (vp->full_bus_master_tx) { /* Free Boomerang bus master Tx buffers. */
2338 for (i = 0; i < TX_RING_SIZE; i++)
2339 if (vp->tx_skbuff[i]) {
2340 struct sk_buff *skb = vp->tx_skbuff[i];
2341
2342 pci_unmap_single(vp->pdev, le32_to_cpu(vp->tx_ring[i].addr), skb->len, PCI_DMA_TODEVICE);
2343 dev_kfree_skb(skb);
2344 vp->tx_skbuff[i] = 0;
2345 }
2346 }
2347
2348 vp->open = 0;
2349 return 0;
2350 }
2351
2352 static void
2353 dump_tx_ring(struct net_device *dev)
2354 {
2355 if (vortex_debug > 0) {
2356 struct vortex_private *vp = (struct vortex_private *)dev->priv;
2357 long ioaddr = dev->base_addr;
2358
2359 if (vp->full_bus_master_tx) {
2360 int i;
2361 int stalled = inl(ioaddr + PktStatus) & 0x04; /* Possible racy. But it's only debug stuff */
2362
2363 wait_for_completion(dev, DownStall);
2364 printk(KERN_ERR " Flags; bus-master %d, full %d; dirty %d(%d) "
2365 "current %d(%d).\n",
2366 vp->full_bus_master_tx, vp->tx_full,
2367 vp->dirty_tx, vp->dirty_tx % TX_RING_SIZE,
2368 vp->cur_tx, vp->cur_tx % TX_RING_SIZE);
2369 printk(KERN_ERR " Transmit list %8.8x vs. %p.\n",
2370 inl(ioaddr + DownListPtr),
2371 &vp->tx_ring[vp->dirty_tx % TX_RING_SIZE]);
2372 for (i = 0; i < TX_RING_SIZE; i++) {
2373 printk(KERN_ERR " %d: @%p length %8.8x status %8.8x\n", i,
2374 &vp->tx_ring[i],
2375 le32_to_cpu(vp->tx_ring[i].length),
2376 le32_to_cpu(vp->tx_ring[i].status));
2377 }
2378 if (!stalled)
2379 outw(DownUnstall, ioaddr + EL3_CMD);
2380 }
2381 }
2382 }
2383
2384 static struct net_device_stats *vortex_get_stats(struct net_device *dev)
2385 {
2386 struct vortex_private *vp = (struct vortex_private *)dev->priv;
2387 unsigned long flags;
2388
2389 if (netif_device_present(dev)) { /* AKPM: Used to be netif_running */
2390 spin_lock_irqsave (&vp->lock, flags);
2391 update_stats(dev->base_addr, dev);
2392 spin_unlock_irqrestore (&vp->lock, flags);
2393 }
2394 return &vp->stats;
2395 }
2396
2397 /* Update statistics.
2398 Unlike with the EL3 we need not worry about interrupts changing
2399 the window setting from underneath us, but we must still guard
2400 against a race condition with a StatsUpdate interrupt updating the
2401 table. This is done by checking that the ASM (!) code generated uses
2402 atomic updates with '+='.
2403 */
2404 static void update_stats(long ioaddr, struct net_device *dev)
2405 {
2406 struct vortex_private *vp = (struct vortex_private *)dev->priv;
2407 int old_window = inw(ioaddr + EL3_CMD);
2408
2409 if (old_window == 0xffff) /* Chip suspended or ejected. */
2410 return;
2411 /* Unlike the 3c5x9 we need not turn off stats updates while reading. */
2412 /* Switch to the stats window, and read everything. */
2413 EL3WINDOW(6);
2414 vp->stats.tx_carrier_errors += inb(ioaddr + 0);
2415 vp->stats.tx_heartbeat_errors += inb(ioaddr + 1);
2416 /* Multiple collisions. */ inb(ioaddr + 2);
2417 vp->stats.collisions += inb(ioaddr + 3);
2418 vp->stats.tx_window_errors += inb(ioaddr + 4);
2419 vp->stats.rx_fifo_errors += inb(ioaddr + 5);
2420 vp->stats.tx_packets += inb(ioaddr + 6);
2421 vp->stats.tx_packets += (inb(ioaddr + 9)&0x30) << 4;
2422 /* Rx packets */ inb(ioaddr + 7); /* Must read to clear */
2423 /* Tx deferrals */ inb(ioaddr + 8);
2424 /* Don't bother with register 9, an extension of registers 6&7.
2425 If we do use the 6&7 values the atomic update assumption above
2426 is invalid. */
2427 vp->stats.rx_bytes += inw(ioaddr + 10);
2428 vp->stats.tx_bytes += inw(ioaddr + 12);
2429 /* New: On the Vortex we must also clear the BadSSD counter. */
2430 EL3WINDOW(4);
2431 inb(ioaddr + 12);
2432
2433 {
2434 u8 up = inb(ioaddr + 13);
2435 vp->stats.rx_bytes += (up & 0x0f) << 16;
2436 vp->stats.tx_bytes += (up & 0xf0) << 12;
2437 }
2438
2439 /* We change back to window 7 (not 1) with the Vortex. */
2440 /* AKPM: the previous comment is obsolete - we switch back to the old window */
2441 EL3WINDOW(old_window >> 13);
2442 return;
2443 }
2444
2445 static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2446 {
2447 struct vortex_private *vp = (struct vortex_private *)dev->priv;
2448 long ioaddr = dev->base_addr;
2449 u16 *data = (u16 *)&rq->ifr_data;
2450 int phy = vp->phys[0] & 0x1f;
2451 int retval;
2452
2453 switch(cmd) {
2454 case SIOCDEVPRIVATE: /* Get the address of the PHY in use. */
2455 data[0] = phy;
2456 case SIOCDEVPRIVATE+1: /* Read the specified MII register. */
2457 EL3WINDOW(4);
2458 data[3] = mdio_read(dev, data[0] & 0x1f, data[1] & 0x1f);
2459 retval = 0;
2460 break;
2461 case SIOCDEVPRIVATE+2: /* Write the specified MII register */
2462 if (!capable(CAP_NET_ADMIN)) {
2463 retval = -EPERM;
2464 } else {
2465 EL3WINDOW(4);
2466 mdio_write(dev, data[0] & 0x1f, data[1] & 0x1f, data[2]);
2467 retval = 0;
2468 }
2469 break;
2470 default:
2471 retval = -EOPNOTSUPP;
2472 break;
2473 }
2474
2475 return retval;
2476 }
2477
2478 /* Pre-Cyclone chips have no documented multicast filter, so the only
2479 multicast setting is to receive all multicast frames. At least
2480 the chip has a very clean way to set the mode, unlike many others. */
2481 static void set_rx_mode(struct net_device *dev)
2482 {
2483 long ioaddr = dev->base_addr;
2484 int new_mode;
2485
2486 if (dev->flags & IFF_PROMISC) {
2487 if (vortex_debug > 0)
2488 printk(KERN_NOTICE "%s: Setting promiscuous mode.\n", dev->name);
2489 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast|RxProm;
2490 } else if ((dev->mc_list) || (dev->flags & IFF_ALLMULTI)) {
2491 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast;
2492 } else
2493 new_mode = SetRxFilter | RxStation | RxBroadcast;
2494
2495 outw(new_mode, ioaddr + EL3_CMD);
2496 }
2497
2498 /* MII transceiver control section.
2499 Read and write the MII registers using software-generated serial
2500 MDIO protocol. See the MII specifications or DP83840A data sheet
2501 for details. */
2502
2503 /* The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
2504 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
2505 "overclocking" issues. */
2506 #define mdio_delay() inl(mdio_addr)
2507
2508 #define MDIO_SHIFT_CLK 0x01
2509 #define MDIO_DIR_WRITE 0x04
2510 #define MDIO_DATA_WRITE0 (0x00 | MDIO_DIR_WRITE)
2511 #define MDIO_DATA_WRITE1 (0x02 | MDIO_DIR_WRITE)
2512 #define MDIO_DATA_READ 0x02
2513 #define MDIO_ENB_IN 0x00
2514
2515 /* Generate the preamble required for initial synchronization and
2516 a few older transceivers. */
2517 static void mdio_sync(long ioaddr, int bits)
2518 {
2519 long mdio_addr = ioaddr + Wn4_PhysicalMgmt;
2520
2521 /* Establish sync by sending at least 32 logic ones. */
2522 while (-- bits >= 0) {
2523 outw(MDIO_DATA_WRITE1, mdio_addr);
2524 mdio_delay();
2525 outw(MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr);
2526 mdio_delay();
2527 }
2528 }
2529
2530 static int mdio_read(struct net_device *dev, int phy_id, int location)
2531 {
2532 struct vortex_private *vp = (struct vortex_private *)dev->priv;
2533 int i;
2534 long ioaddr = dev->base_addr;
2535 int read_cmd = (0xf6 << 10) | (phy_id << 5) | location;
2536 unsigned int retval = 0;
2537 long mdio_addr = ioaddr + Wn4_PhysicalMgmt;
2538
2539 spin_lock_bh(&vp->mdio_lock);
2540
2541 if (mii_preamble_required)
2542 mdio_sync(ioaddr, 32);
2543
2544 /* Shift the read command bits out. */
2545 for (i = 14; i >= 0; i--) {
2546 int dataval = (read_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
2547 outw(dataval, mdio_addr);
2548 mdio_delay();
2549 outw(dataval | MDIO_SHIFT_CLK, mdio_addr);
2550 mdio_delay();
2551 }
2552 /* Read the two transition, 16 data, and wire-idle bits. */
2553 for (i = 19; i > 0; i--) {
2554 outw(MDIO_ENB_IN, mdio_addr);
2555 mdio_delay();
2556 retval = (retval << 1) | ((inw(mdio_addr) & MDIO_DATA_READ) ? 1 : 0);
2557 outw(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
2558 mdio_delay();
2559 }
2560 spin_unlock_bh(&vp->mdio_lock);
2561 return retval & 0x20000 ? 0xffff : retval>>1 & 0xffff;
2562 }
2563
2564 static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
2565 {
2566 struct vortex_private *vp = (struct vortex_private *)dev->priv;
2567 long ioaddr = dev->base_addr;
2568 int write_cmd = 0x50020000 | (phy_id << 23) | (location << 18) | value;
2569 long mdio_addr = ioaddr + Wn4_PhysicalMgmt;
2570 int i;
2571
2572 spin_lock_bh(&vp->mdio_lock);
2573
2574 if (mii_preamble_required)
2575 mdio_sync(ioaddr, 32);
2576
2577 /* Shift the command bits out. */
2578 for (i = 31; i >= 0; i--) {
2579 int dataval = (write_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
2580 outw(dataval, mdio_addr);
2581 mdio_delay();
2582 outw(dataval | MDIO_SHIFT_CLK, mdio_addr);
2583 mdio_delay();
2584 }
2585 /* Leave the interface idle. */
2586 for (i = 1; i >= 0; i--) {
2587 outw(MDIO_ENB_IN, mdio_addr);
2588 mdio_delay();
2589 outw(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
2590 mdio_delay();
2591 }
2592 spin_unlock_bh(&vp->mdio_lock);
2593 return;
2594 }
2595
2596 /* ACPI: Advanced Configuration and Power Interface. */
2597 /* Set Wake-On-LAN mode and put the board into D3 (power-down) state. */
2598 static void acpi_set_WOL(struct net_device *dev)
2599 {
2600 struct vortex_private *vp = (struct vortex_private *)dev->priv;
2601 long ioaddr = dev->base_addr;
2602
2603 /* AKPM: This kills the 905 */
2604 if (vortex_debug > 1) {
2605 printk(KERN_INFO PFX "Wake-on-LAN functions disabled\n");
2606 }
2607 return;
2608
2609 /* Power up on: 1==Downloaded Filter, 2==Magic Packets, 4==Link Status. */
2610 EL3WINDOW(7);
2611 outw(2, ioaddr + 0x0c);
2612 /* The RxFilter must accept the WOL frames. */
2613 outw(SetRxFilter|RxStation|RxMulticast|RxBroadcast, ioaddr + EL3_CMD);
2614 outw(RxEnable, ioaddr + EL3_CMD);
2615 /* Change the power state to D3; RxEnable doesn't take effect. */
2616 pci_write_config_word(vp->pdev, 0xe0, 0x8103);
2617 }
2618
2619
2620 static void __devexit vortex_remove_one (struct pci_dev *pdev)
2621 {
2622 struct net_device *dev = pdev->driver_data;
2623 struct vortex_private *vp;
2624
2625 if (!dev) {
2626 printk("vortex_remove_one called for EISA device!\n");
2627 BUG();
2628 }
2629
2630 vp = (void *)(dev->priv);
2631
2632 /* AKPM: FIXME: we should have
2633 * if (vp->cb_fn_base) iounmap(vp->cb_fn_base);
2634 * here
2635 */
2636 unregister_netdev(dev);
2637 outw(TotalReset, dev->base_addr + EL3_CMD);
2638 if (vp->must_free_region)
2639 release_region(dev->base_addr, vp->io_size);
2640 kfree(dev);
2641 }
2642
2643
2644 static struct pci_driver vortex_driver = {
2645 name: "3c575_cb",
2646 probe: vortex_init_one,
2647 remove: vortex_remove_one,
2648 suspend: vortex_suspend,
2649 resume: vortex_resume,
2650 id_table: vortex_pci_tbl,
2651 };
2652
2653
2654 static int vortex_have_pci;
2655 static int vortex_have_eisa;
2656
2657
2658 static int __init vortex_init (void)
2659 {
2660 int rc;
2661
2662 rc = pci_module_init(&vortex_driver);
2663 if (rc < 0) {
2664 rc = vortex_eisa_init();
2665 if (rc > 0)
2666 vortex_have_eisa = 1;
2667 } else {
2668 vortex_have_pci = 1;
2669 }
2670
2671 return rc;
2672 }
2673
2674
2675 static void __exit vortex_eisa_cleanup (void)
2676 {
2677 struct net_device *dev, *tmp;
2678 struct vortex_private *vp;
2679 long ioaddr;
2680
2681 dev = root_vortex_eisa_dev;
2682
2683 while (dev) {
2684 vp = dev->priv;
2685 ioaddr = dev->base_addr;
2686
2687 unregister_netdev (dev);
2688 outw (TotalReset, ioaddr + EL3_CMD);
2689 release_region (ioaddr, VORTEX_TOTAL_SIZE);
2690
2691 tmp = dev;
2692 dev = vp->next_module;
2693
2694 kfree (tmp);
2695 }
2696 }
2697
2698
2699 static void __exit vortex_cleanup (void)
2700 {
2701 if (vortex_have_pci)
2702 pci_unregister_driver (&vortex_driver);
2703 if (vortex_have_eisa)
2704 vortex_eisa_cleanup ();
2705 }
2706
2707
2708 module_init(vortex_init);
2709 module_exit(vortex_cleanup);
2710
2711
2712
2713 /*
2714 * Local variables:
2715 * c-indent-level: 4
2716 * c-basic-offset: 4
2717 * tab-width: 4
2718 * End:
2719 */
2720
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