1 /*
2 * linux/drivers/ide/pdc202xx.c Version 0.30 Mar. 18, 2000
3 *
4 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
5 * May be copied or modified under the terms of the GNU General Public License
6 *
7 * Promise Ultra33 cards with BIOS v1.20 through 1.28 will need this
8 * compiled into the kernel if you have more than one card installed.
9 * Note that BIOS v1.29 is reported to fix the problem. Since this is
10 * safe chipset tuning, including this support is harmless
11 *
12 * Promise Ultra66 cards with BIOS v1.11 this
13 * compiled into the kernel if you have more than one card installed.
14 *
15 * Promise Ultra100 cards.
16 *
17 * The latest chipset code will support the following ::
18 * Three Ultra33 controllers and 12 drives.
19 * 8 are UDMA supported and 4 are limited to DMA mode 2 multi-word.
20 * The 8/4 ratio is a BIOS code limit by promise.
21 *
22 * UNLESS you enable "CONFIG_PDC202XX_BURST"
23 *
24 */
25
26 /*
27 * Portions Copyright (C) 1999 Promise Technology, Inc.
28 * Author: Frank Tiernan (frankt@promise.com)
29 * Released under terms of General Public License
30 */
31
32 #include <linux/config.h>
33 #include <linux/types.h>
34 #include <linux/kernel.h>
35 #include <linux/delay.h>
36 #include <linux/timer.h>
37 #include <linux/mm.h>
38 #include <linux/ioport.h>
39 #include <linux/blkdev.h>
40 #include <linux/hdreg.h>
41 #include <linux/interrupt.h>
42 #include <linux/pci.h>
43 #include <linux/init.h>
44 #include <linux/ide.h>
45
46 #include <asm/io.h>
47 #include <asm/irq.h>
48
49 #include "ide_modes.h"
50
51 #define PDC202XX_DEBUG_DRIVE_INFO 0
52 #define PDC202XX_DECODE_REGISTER_INFO 0
53
54 #define DISPLAY_PDC202XX_TIMINGS
55
56 #ifndef SPLIT_BYTE
57 #define SPLIT_BYTE(B,H,L) ((H)=(B>>4), (L)=(B-((B>>4)<<4)))
58 #endif
59
60 #if defined(DISPLAY_PDC202XX_TIMINGS) && defined(CONFIG_PROC_FS)
61 #include <linux/stat.h>
62 #include <linux/proc_fs.h>
63
64 static int pdc202xx_get_info(char *, char **, off_t, int);
65 extern int (*pdc202xx_display_info)(char *, char **, off_t, int); /* ide-proc.c */
66 extern char *ide_media_verbose(ide_drive_t *);
67 static struct pci_dev *bmide_dev;
68
69 char *pdc202xx_pio_verbose (u32 drive_pci)
70 {
71 if ((drive_pci & 0x000ff000) == 0x000ff000) return("NOTSET");
72 if ((drive_pci & 0x00000401) == 0x00000401) return("PIO 4");
73 if ((drive_pci & 0x00000602) == 0x00000602) return("PIO 3");
74 if ((drive_pci & 0x00000803) == 0x00000803) return("PIO 2");
75 if ((drive_pci & 0x00000C05) == 0x00000C05) return("PIO 1");
76 if ((drive_pci & 0x00001309) == 0x00001309) return("PIO 0");
77 return("PIO ?");
78 }
79
80 char *pdc202xx_dma_verbose (u32 drive_pci)
81 {
82 if ((drive_pci & 0x00036000) == 0x00036000) return("MWDMA 2");
83 if ((drive_pci & 0x00046000) == 0x00046000) return("MWDMA 1");
84 if ((drive_pci & 0x00056000) == 0x00056000) return("MWDMA 0");
85 if ((drive_pci & 0x00056000) == 0x00056000) return("SWDMA 2");
86 if ((drive_pci & 0x00068000) == 0x00068000) return("SWDMA 1");
87 if ((drive_pci & 0x000BC000) == 0x000BC000) return("SWDMA 0");
88 return("PIO---");
89 }
90
91 char *pdc202xx_ultra_verbose (u32 drive_pci, u16 slow_cable)
92 {
93 if ((drive_pci & 0x000ff000) == 0x000ff000)
94 return("NOTSET");
95 if ((drive_pci & 0x00012000) == 0x00012000)
96 return((slow_cable) ? "UDMA 2" : "UDMA 4");
97 if ((drive_pci & 0x00024000) == 0x00024000)
98 return((slow_cable) ? "UDMA 1" : "UDMA 3");
99 if ((drive_pci & 0x00036000) == 0x00036000)
100 return("UDMA 0");
101 return(pdc202xx_dma_verbose(drive_pci));
102 }
103
104 char *pdc202xx_interrupt_verbose (u8 sc1d)
105 {
106 char *p = NULL;
107 p += sprintf(p,"0x%02x ", sc1d);
108 return (char *)p;
109 }
110
111 static char * pdc202xx_info (char *buf, struct pci_dev *dev)
112 {
113 char *p = buf;
114
115 u32 bibma = pci_resource_start(dev, 4);
116 u32 reg60h = 0, reg64h = 0, reg68h = 0, reg6ch = 0;
117 u16 reg50h = 0, pmask = (1<<10), smask = (1<<11);
118 u8 hi = 0, lo = 0;
119
120 /*
121 * at that point bibma+0x2 et bibma+0xa are byte registers
122 * to investigate:
123 */
124 u8 c0 = inb_p((unsigned short)bibma + 0x02);
125 u8 c1 = inb_p((unsigned short)bibma + 0x0a);
126
127 u8 sc11 = inb_p((unsigned short)bibma + 0x11);
128 u8 sc1a = inb_p((unsigned short)bibma + 0x1a);
129 u8 sc1b = inb_p((unsigned short)bibma + 0x1b);
130 u8 sc1c = inb_p((unsigned short)bibma + 0x1c);
131 u8 sc1d = inb_p((unsigned short)bibma + 0x1d);
132 u8 sc1e = inb_p((unsigned short)bibma + 0x1e);
133 u8 sc1f = inb_p((unsigned short)bibma + 0x1f);
134
135 pci_read_config_word(dev, 0x50, ®50h);
136 pci_read_config_dword(dev, 0x60, ®60h);
137 pci_read_config_dword(dev, 0x64, ®64h);
138 pci_read_config_dword(dev, 0x68, ®68h);
139 pci_read_config_dword(dev, 0x6c, ®6ch);
140
141 switch(dev->device) {
142 case PCI_DEVICE_ID_PROMISE_20267:
143 p += sprintf(p, "\n PDC20267 Chipset.\n");
144 break;
145 case PCI_DEVICE_ID_PROMISE_20265:
146 p += sprintf(p, "\n PDC20265 Chipset.\n");
147 break;
148 case PCI_DEVICE_ID_PROMISE_20262:
149 p += sprintf(p, "\n PDC20262 Chipset.\n");
150 break;
151 case PCI_DEVICE_ID_PROMISE_20246:
152 p += sprintf(p, "\n PDC20246 Chipset.\n");
153 reg50h |= 0x0c00;
154 break;
155 default:
156 p += sprintf(p, "\n PDC202XX Chipset.\n");
157 break;
158 }
159
160 p += sprintf(p, "------------------------------- General Status ---------------------------------\n");
161 p += sprintf(p, "Burst Mode : %sabled\n", (sc1f & 0x01) ? "en" : "dis");
162 p += sprintf(p, "Host Mode : %s\n", (sc1f & 0x08) ? "Tri-Stated" : "Normal");
163 p += sprintf(p, "Bus Clocking : %s\n",
164 ((sc1f & 0xC0) == 0xC0) ? "100 External" :
165 ((sc1f & 0x80) == 0x80) ? "66 External" :
166 ((sc1f & 0x40) == 0x40) ? "33 External" : "33 PCI Internal");
167 p += sprintf(p, "IO pad select : %s mA\n",
168 ((sc1c & 0x03) == 0x03) ? "10" :
169 ((sc1c & 0x02) == 0x02) ? "8" :
170 ((sc1c & 0x01) == 0x01) ? "6" :
171 ((sc1c & 0x00) == 0x00) ? "4" : "??");
172 SPLIT_BYTE(sc1e, hi, lo);
173 p += sprintf(p, "Status Polling Period : %d\n", hi);
174 p += sprintf(p, "Interrupt Check Status Polling Delay : %d\n", lo);
175 p += sprintf(p, "--------------- Primary Channel ---------------- Secondary Channel -------------\n");
176 p += sprintf(p, " %s %s\n",
177 (c0&0x80)?"disabled":"enabled ",
178 (c1&0x80)?"disabled":"enabled ");
179 p += sprintf(p, "66 Clocking %s %s\n",
180 (sc11&0x02)?"enabled ":"disabled",
181 (sc11&0x08)?"enabled ":"disabled");
182 p += sprintf(p, " Mode %s Mode %s\n",
183 (sc1a & 0x01) ? "MASTER" : "PCI ",
184 (sc1b & 0x01) ? "MASTER" : "PCI ");
185 p += sprintf(p, " %s %s\n",
186 (sc1d & 0x08) ? "Error " :
187 ((sc1d & 0x05) == 0x05) ? "Not My INTR " :
188 (sc1d & 0x04) ? "Interrupting" :
189 (sc1d & 0x02) ? "FIFO Full " :
190 (sc1d & 0x01) ? "FIFO Empty " : "????????????",
191 (sc1d & 0x80) ? "Error " :
192 ((sc1d & 0x50) == 0x50) ? "Not My INTR " :
193 (sc1d & 0x40) ? "Interrupting" :
194 (sc1d & 0x20) ? "FIFO Full " :
195 (sc1d & 0x10) ? "FIFO Empty " : "????????????");
196 p += sprintf(p, "--------------- drive0 --------- drive1 -------- drive0 ---------- drive1 ------\n");
197 p += sprintf(p, "DMA enabled: %s %s %s %s\n",
198 (c0&0x20)?"yes":"no ",(c0&0x40)?"yes":"no ",(c1&0x20)?"yes":"no ",(c1&0x40)?"yes":"no ");
199 p += sprintf(p, "DMA Mode: %s %s %s %s\n",
200 pdc202xx_ultra_verbose(reg60h, (reg50h & pmask)),
201 pdc202xx_ultra_verbose(reg64h, (reg50h & pmask)),
202 pdc202xx_ultra_verbose(reg68h, (reg50h & smask)),
203 pdc202xx_ultra_verbose(reg6ch, (reg50h & smask)));
204 p += sprintf(p, "PIO Mode: %s %s %s %s\n",
205 pdc202xx_pio_verbose(reg60h),pdc202xx_pio_verbose(reg64h),
206 pdc202xx_pio_verbose(reg68h),pdc202xx_pio_verbose(reg6ch));
207 #if 0
208 p += sprintf(p, "--------------- Can ATAPI DMA ---------------\n");
209 #endif
210 return (char *)p;
211 }
212
213 static int pdc202xx_get_info (char *buffer, char **addr, off_t offset, int count)
214 {
215 char *p = buffer;
216 p = pdc202xx_info(buffer, bmide_dev);
217 return p-buffer; /* => must be less than 4k! */
218 }
219 #endif /* defined(DISPLAY_PDC202XX_TIMINGS) && defined(CONFIG_PROC_FS) */
220
221 byte pdc202xx_proc = 0;
222
223 const char *pdc_quirk_drives[] = {
224 "QUANTUM FIREBALLlct08 08",
225 "QUANTUM FIREBALLP KA6.4",
226 "QUANTUM FIREBALLP LM20.4",
227 "QUANTUM FIREBALLP LM20.5",
228 NULL
229 };
230
231 extern char *ide_xfer_verbose (byte xfer_rate);
232
233 /* A Register */
234 #define SYNC_ERRDY_EN 0xC0
235
236 #define SYNC_IN 0x80 /* control bit, different for master vs. slave drives */
237 #define ERRDY_EN 0x40 /* control bit, different for master vs. slave drives */
238 #define IORDY_EN 0x20 /* PIO: IOREADY */
239 #define PREFETCH_EN 0x10 /* PIO: PREFETCH */
240
241 #define PA3 0x08 /* PIO"A" timing */
242 #define PA2 0x04 /* PIO"A" timing */
243 #define PA1 0x02 /* PIO"A" timing */
244 #define PA0 0x01 /* PIO"A" timing */
245
246 /* B Register */
247
248 #define MB2 0x80 /* DMA"B" timing */
249 #define MB1 0x40 /* DMA"B" timing */
250 #define MB0 0x20 /* DMA"B" timing */
251
252 #define PB4 0x10 /* PIO_FORCE 1:0 */
253
254 #define PB3 0x08 /* PIO"B" timing */ /* PIO flow Control mode */
255 #define PB2 0x04 /* PIO"B" timing */ /* PIO 4 */
256 #define PB1 0x02 /* PIO"B" timing */ /* PIO 3 half */
257 #define PB0 0x01 /* PIO"B" timing */ /* PIO 3 other half */
258
259 /* C Register */
260 #define IORDYp_NO_SPEED 0x4F
261 #define SPEED_DIS 0x0F
262
263 #define DMARQp 0x80
264 #define IORDYp 0x40
265 #define DMAR_EN 0x20
266 #define DMAW_EN 0x10
267
268 #define MC3 0x08 /* DMA"C" timing */
269 #define MC2 0x04 /* DMA"C" timing */
270 #define MC1 0x02 /* DMA"C" timing */
271 #define MC0 0x01 /* DMA"C" timing */
272
273 #if PDC202XX_DECODE_REGISTER_INFO
274
275 #define REG_A 0x01
276 #define REG_B 0x02
277 #define REG_C 0x04
278 #define REG_D 0x08
279
280 static void decode_registers (byte registers, byte value)
281 {
282 byte bit = 0, bit1 = 0, bit2 = 0;
283
284 switch(registers) {
285 case REG_A:
286 bit2 = 0;
287 printk("A Register ");
288 if (value & 0x80) printk("SYNC_IN ");
289 if (value & 0x40) printk("ERRDY_EN ");
290 if (value & 0x20) printk("IORDY_EN ");
291 if (value & 0x10) printk("PREFETCH_EN ");
292 if (value & 0x08) { printk("PA3 ");bit2 |= 0x08; }
293 if (value & 0x04) { printk("PA2 ");bit2 |= 0x04; }
294 if (value & 0x02) { printk("PA1 ");bit2 |= 0x02; }
295 if (value & 0x01) { printk("PA0 ");bit2 |= 0x01; }
296 printk("PIO(A) = %d ", bit2);
297 break;
298 case REG_B:
299 bit1 = 0;bit2 = 0;
300 printk("B Register ");
301 if (value & 0x80) { printk("MB2 ");bit1 |= 0x80; }
302 if (value & 0x40) { printk("MB1 ");bit1 |= 0x40; }
303 if (value & 0x20) { printk("MB0 ");bit1 |= 0x20; }
304 printk("DMA(B) = %d ", bit1 >> 5);
305 if (value & 0x10) printk("PIO_FORCED/PB4 ");
306 if (value & 0x08) { printk("PB3 ");bit2 |= 0x08; }
307 if (value & 0x04) { printk("PB2 ");bit2 |= 0x04; }
308 if (value & 0x02) { printk("PB1 ");bit2 |= 0x02; }
309 if (value & 0x01) { printk("PB0 ");bit2 |= 0x01; }
310 printk("PIO(B) = %d ", bit2);
311 break;
312 case REG_C:
313 bit2 = 0;
314 printk("C Register ");
315 if (value & 0x80) printk("DMARQp ");
316 if (value & 0x40) printk("IORDYp ");
317 if (value & 0x20) printk("DMAR_EN ");
318 if (value & 0x10) printk("DMAW_EN ");
319
320 if (value & 0x08) { printk("MC3 ");bit2 |= 0x08; }
321 if (value & 0x04) { printk("MC2 ");bit2 |= 0x04; }
322 if (value & 0x02) { printk("MC1 ");bit2 |= 0x02; }
323 if (value & 0x01) { printk("MC0 ");bit2 |= 0x01; }
324 printk("DMA(C) = %d ", bit2);
325 break;
326 case REG_D:
327 printk("D Register ");
328 break;
329 default:
330 return;
331 }
332 printk("\n %s ", (registers & REG_D) ? "DP" :
333 (registers & REG_C) ? "CP" :
334 (registers & REG_B) ? "BP" :
335 (registers & REG_A) ? "AP" : "ERROR");
336 for (bit=128;bit>0;bit/=2)
337 printk("%s", (value & bit) ? "1" : "");
338 printk("\n");
339 }
340
341 #endif /* PDC202XX_DECODE_REGISTER_INFO */
342
343 static int check_in_drive_lists (ide_drive_t *drive, const char **list)
344 {
345 struct hd_driveid *id = drive->id;
346
347 if (pdc_quirk_drives == list) {
348 while (*list) {
349 if (strstr(id->model, *list++)) {
350 return 2;
351 }
352 }
353 } else {
354 while (*list) {
355 if (!strcmp(*list++,id->model)) {
356 return 1;
357 }
358 }
359 }
360 return 0;
361 }
362
363 static int pdc202xx_tune_chipset (ide_drive_t *drive, byte speed)
364 {
365 ide_hwif_t *hwif = HWIF(drive);
366 struct pci_dev *dev = hwif->pci_dev;
367
368 unsigned int drive_conf;
369 int err;
370 byte drive_pci, AP, BP, CP, DP;
371 byte TA = 0, TB = 0, TC = 0;
372
373 switch (drive->dn) {
374 case 0: drive_pci = 0x60; break;
375 case 1: drive_pci = 0x64; break;
376 case 2: drive_pci = 0x68; break;
377 case 3: drive_pci = 0x6c; break;
378 default: return -1;
379 }
380
381 if ((drive->media != ide_disk) && (speed < XFER_SW_DMA_0)) return -1;
382
383 pci_read_config_dword(dev, drive_pci, &drive_conf);
384 pci_read_config_byte(dev, (drive_pci), &AP);
385 pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
386 pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
387 pci_read_config_byte(dev, (drive_pci)|0x03, &DP);
388
389 #ifdef CONFIG_BLK_DEV_IDEDMA
390 if (speed >= XFER_SW_DMA_0) {
391 if ((BP & 0xF0) && (CP & 0x0F)) {
392 /* clear DMA modes of upper 842 bits of B Register */
393 /* clear PIO forced mode upper 1 bit of B Register */
394 pci_write_config_byte(dev, (drive_pci)|0x01, BP & ~0xF0);
395 pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
396
397 /* clear DMA modes of lower 8421 bits of C Register */
398 pci_write_config_byte(dev, (drive_pci)|0x02, CP & ~0x0F);
399 pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
400 }
401 } else {
402 #else
403 {
404 #endif /* CONFIG_BLK_DEV_IDEDMA */
405 if ((AP & 0x0F) || (BP & 0x07)) {
406 /* clear PIO modes of lower 8421 bits of A Register */
407 pci_write_config_byte(dev, (drive_pci), AP & ~0x0F);
408 pci_read_config_byte(dev, (drive_pci), &AP);
409
410 /* clear PIO modes of lower 421 bits of B Register */
411 pci_write_config_byte(dev, (drive_pci)|0x01, BP & ~0x07);
412 pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
413
414 pci_read_config_byte(dev, (drive_pci), &AP);
415 pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
416 }
417 }
418
419 pci_read_config_byte(dev, (drive_pci), &AP);
420 pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
421 pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
422
423 switch(speed) {
424 #ifdef CONFIG_BLK_DEV_IDEDMA
425 case XFER_UDMA_5:
426 case XFER_UDMA_4: TB = 0x20; TC = 0x01; break; /* speed 8 == UDMA mode 4 */
427 case XFER_UDMA_3: TB = 0x40; TC = 0x02; break; /* speed 7 == UDMA mode 3 */
428 case XFER_UDMA_2: TB = 0x20; TC = 0x01; break; /* speed 6 == UDMA mode 2 */
429 case XFER_UDMA_1: TB = 0x40; TC = 0x02; break; /* speed 5 == UDMA mode 1 */
430 case XFER_UDMA_0: TB = 0x60; TC = 0x03; break; /* speed 4 == UDMA mode 0 */
431 case XFER_MW_DMA_2: TB = 0x60; TC = 0x03; break; /* speed 4 == MDMA mode 2 */
432 case XFER_MW_DMA_1: TB = 0x60; TC = 0x04; break; /* speed 3 == MDMA mode 1 */
433 case XFER_MW_DMA_0: TB = 0x60; TC = 0x05; break; /* speed 2 == MDMA mode 0 */
434 case XFER_SW_DMA_2: TB = 0x60; TC = 0x05; break; /* speed 0 == SDMA mode 2 */
435 case XFER_SW_DMA_1: TB = 0x80; TC = 0x06; break; /* speed 1 == SDMA mode 1 */
436 case XFER_SW_DMA_0: TB = 0xC0; TC = 0x0B; break; /* speed 0 == SDMA mode 0 */
437 #endif /* CONFIG_BLK_DEV_IDEDMA */
438 case XFER_PIO_4: TA = 0x01; TB = 0x04; break;
439 case XFER_PIO_3: TA = 0x02; TB = 0x06; break;
440 case XFER_PIO_2: TA = 0x03; TB = 0x08; break;
441 case XFER_PIO_1: TA = 0x05; TB = 0x0C; break;
442 case XFER_PIO_0:
443 default: TA = 0x09; TB = 0x13; break;
444 }
445
446 #ifdef CONFIG_BLK_DEV_IDEDMA
447 if (speed >= XFER_SW_DMA_0) {
448 pci_write_config_byte(dev, (drive_pci)|0x01, BP|TB);
449 pci_write_config_byte(dev, (drive_pci)|0x02, CP|TC);
450 } else {
451 #else
452 {
453 #endif /* CONFIG_BLK_DEV_IDEDMA */
454 pci_write_config_byte(dev, (drive_pci), AP|TA);
455 pci_write_config_byte(dev, (drive_pci)|0x01, BP|TB);
456 }
457
458 #if PDC202XX_DECODE_REGISTER_INFO
459 pci_read_config_byte(dev, (drive_pci), &AP);
460 pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
461 pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
462 pci_read_config_byte(dev, (drive_pci)|0x03, &DP);
463
464 decode_registers(REG_A, AP);
465 decode_registers(REG_B, BP);
466 decode_registers(REG_C, CP);
467 decode_registers(REG_D, DP);
468 #endif /* PDC202XX_DECODE_REGISTER_INFO */
469
470 err = ide_config_drive_speed(drive, speed);
471
472 #if PDC202XX_DEBUG_DRIVE_INFO
473 printk("%s: %s drive%d 0x%08x ",
474 drive->name, ide_xfer_verbose(speed),
475 drive->dn, drive_conf);
476 pci_read_config_dword(dev, drive_pci, &drive_conf);
477 printk("0x%08x\n", drive_conf);
478 #endif /* PDC202XX_DEBUG_DRIVE_INFO */
479 return err;
480 }
481
482 /* 0 1 2 3 4 5 6 7 8
483 * 960, 480, 390, 300, 240, 180, 120, 90, 60
484 * 180, 150, 120, 90, 60
485 * DMA_Speed
486 * 180, 120, 90, 90, 90, 60, 30
487 * 11, 5, 4, 3, 2, 1, 0
488 */
489 static int config_chipset_for_pio (ide_drive_t *drive, byte pio)
490 {
491 byte speed = 0x00;
492
493 pio = (pio == 5) ? 4 : pio;
494 speed = XFER_PIO_0 + ide_get_best_pio_mode(drive, 255, pio, NULL);
495
496 return ((int) pdc202xx_tune_chipset(drive, speed));
497 }
498
499 static void pdc202xx_tune_drive (ide_drive_t *drive, byte pio)
500 {
501 (void) config_chipset_for_pio(drive, pio);
502 }
503
504 #ifdef CONFIG_BLK_DEV_IDEDMA
505 static int config_chipset_for_dma (ide_drive_t *drive, byte ultra)
506 {
507 struct hd_driveid *id = drive->id;
508 ide_hwif_t *hwif = HWIF(drive);
509 struct pci_dev *dev = hwif->pci_dev;
510 unsigned long high_16 = pci_resource_start(dev, 4);
511 unsigned long dma_base = hwif->dma_base;
512 byte unit = (drive->select.b.unit & 0x01);
513
514 unsigned int drive_conf;
515 byte drive_pci;
516 byte test1, test2, speed = -1;
517 byte AP;
518 unsigned short EP;
519 byte CLKSPD = IN_BYTE(high_16 + 0x11);
520 byte udma_33 = ultra ? (inb(high_16 + 0x001f) & 1) : 0;
521 byte udma_66 = ((eighty_ninty_three(drive)) && udma_33) ? 1 : 0;
522 byte udma_100 = (((dev->device == PCI_DEVICE_ID_PROMISE_20265) || (dev->device == PCI_DEVICE_ID_PROMISE_20267)) && udma_66) ? 1 : 0;
523
524 /*
525 * Set the control register to use the 66Mhz system
526 * clock for UDMA 3/4 mode operation. If one drive on
527 * a channel is U66 capable but the other isn't we
528 * fall back to U33 mode. The BIOS INT 13 hooks turn
529 * the clock on then off for each read/write issued. I don't
530 * do that here because it would require modifying the
531 * kernel, seperating the fop routines from the kernel or
532 * somehow hooking the fops calls. It may also be possible to
533 * leave the 66Mhz clock on and readjust the timing
534 * parameters.
535 */
536
537 byte mask = hwif->channel ? 0x08 : 0x02;
538 unsigned short c_mask = hwif->channel ? (1<<11) : (1<<10);
539 byte ultra_66 = ((id->dma_ultra & 0x0010) ||
540 (id->dma_ultra & 0x0008)) ? 1 : 0;
541 byte ultra_100 = ((id->dma_ultra & 0x0020) ||
542 (id->dma_ultra & 0x0010) ||
543 (id->dma_ultra & 0x0008)) ? 1 : 0;
544
545 pci_read_config_word(dev, 0x50, &EP);
546
547 if (((ultra_66) || (ultra_100)) && (EP & c_mask)) {
548 #ifdef DEBUG
549 printk("ULTRA66: %s channel of Ultra 66 requires an 80-pin cable for Ultra66 operation.\n", hwif->channel ? "Secondary", "Primary");
550 printk(" Switching to Ultra33 mode.\n");
551 #endif /* DEBUG */
552 /* Primary : zero out second bit */
553 /* Secondary : zero out fourth bit */
554 OUT_BYTE(CLKSPD & ~mask, (high_16 + 0x11));
555 } else {
556 if ((ultra_66) || (ultra_100)) {
557 /*
558 * check to make sure drive on same channel
559 * is u66 capable
560 */
561 if (hwif->drives[!(drive->dn%2)].id) {
562 if ((hwif->drives[!(drive->dn%2)].id->dma_ultra & 0x0020) ||
563 (hwif->drives[!(drive->dn%2)].id->dma_ultra & 0x0010) ||
564 (hwif->drives[!(drive->dn%2)].id->dma_ultra & 0x0008)) {
565 OUT_BYTE(CLKSPD | mask, (high_16 + 0x11));
566 } else {
567 OUT_BYTE(CLKSPD & ~mask, (high_16 + 0x11));
568 }
569 } else { /* udma4 drive by itself */
570 OUT_BYTE(CLKSPD | mask, (high_16 + 0x11));
571 }
572 }
573 }
574
575 switch(drive->dn) {
576 case 0: drive_pci = 0x60;
577 pci_read_config_dword(dev, drive_pci, &drive_conf);
578 if ((drive_conf != 0x004ff304) && (drive_conf != 0x004ff3c4))
579 goto chipset_is_set;
580 pci_read_config_byte(dev, (drive_pci), &test1);
581 if (!(test1 & SYNC_ERRDY_EN))
582 pci_write_config_byte(dev, (drive_pci), test1|SYNC_ERRDY_EN);
583 break;
584 case 1: drive_pci = 0x64;
585 pci_read_config_dword(dev, drive_pci, &drive_conf);
586 if ((drive_conf != 0x004ff304) && (drive_conf != 0x004ff3c4))
587 goto chipset_is_set;
588 pci_read_config_byte(dev, 0x60, &test1);
589 pci_read_config_byte(dev, (drive_pci), &test2);
590 if ((test1 & SYNC_ERRDY_EN) && !(test2 & SYNC_ERRDY_EN))
591 pci_write_config_byte(dev, (drive_pci), test2|SYNC_ERRDY_EN);
592 break;
593 case 2: drive_pci = 0x68;
594 pci_read_config_dword(dev, drive_pci, &drive_conf);
595 if ((drive_conf != 0x004ff304) && (drive_conf != 0x004ff3c4))
596 goto chipset_is_set;
597 pci_read_config_byte(dev, (drive_pci), &test1);
598 if (!(test1 & SYNC_ERRDY_EN))
599 pci_write_config_byte(dev, (drive_pci), test1|SYNC_ERRDY_EN);
600 break;
601 case 3: drive_pci = 0x6c;
602 pci_read_config_dword(dev, drive_pci, &drive_conf);
603 if ((drive_conf != 0x004ff304) && (drive_conf != 0x004ff3c4))
604 goto chipset_is_set;
605 pci_read_config_byte(dev, 0x68, &test1);
606 pci_read_config_byte(dev, (drive_pci), &test2);
607 if ((test1 & SYNC_ERRDY_EN) && !(test2 & SYNC_ERRDY_EN))
608 pci_write_config_byte(dev, (drive_pci), test2|SYNC_ERRDY_EN);
609 break;
610 default:
611 return ide_dma_off;
612 }
613
614 chipset_is_set:
615
616 if (drive->media != ide_disk) return ide_dma_off_quietly;
617
618 pci_read_config_byte(dev, (drive_pci), &AP);
619 if (id->capability & 4) /* IORDY_EN */
620 pci_write_config_byte(dev, (drive_pci), AP|IORDY_EN);
621 pci_read_config_byte(dev, (drive_pci), &AP);
622 if (drive->media == ide_disk) /* PREFETCH_EN */
623 pci_write_config_byte(dev, (drive_pci), AP|PREFETCH_EN);
624
625 if ((id->dma_ultra & 0x0020) && (udma_100)) speed = XFER_UDMA_5;
626 else if ((id->dma_ultra & 0x0010) && (udma_66)) speed = XFER_UDMA_4;
627 else if ((id->dma_ultra & 0x0008) && (udma_66)) speed = XFER_UDMA_3;
628 else if ((id->dma_ultra & 0x0004) && (udma_33)) speed = XFER_UDMA_2;
629 else if ((id->dma_ultra & 0x0002) && (udma_33)) speed = XFER_UDMA_1;
630 else if ((id->dma_ultra & 0x0001) && (udma_33)) speed = XFER_UDMA_0;
631 else if (id->dma_mword & 0x0004) speed = XFER_MW_DMA_2;
632 else if (id->dma_mword & 0x0002) speed = XFER_MW_DMA_1;
633 else if (id->dma_mword & 0x0001) speed = XFER_MW_DMA_0;
634 else if (id->dma_1word & 0x0004) speed = XFER_SW_DMA_2;
635 else if (id->dma_1word & 0x0002) speed = XFER_SW_DMA_1;
636 else if (id->dma_1word & 0x0001) speed = XFER_SW_DMA_0;
637 else {
638 /* restore original pci-config space */
639 pci_write_config_dword(dev, drive_pci, drive_conf);
640 return ide_dma_off_quietly;
641 }
642
643 outb(inb(dma_base+2) & ~(1<<(5+unit)), dma_base+2);
644 (void) pdc202xx_tune_chipset(drive, speed);
645
646 return ((int) ((id->dma_ultra >> 11) & 7) ? ide_dma_on :
647 ((id->dma_ultra >> 8) & 7) ? ide_dma_on :
648 ((id->dma_mword >> 8) & 7) ? ide_dma_on :
649 ((id->dma_1word >> 8) & 7) ? ide_dma_on :
650 ide_dma_off_quietly);
651 }
652
653 static int config_drive_xfer_rate (ide_drive_t *drive)
654 {
655 struct hd_driveid *id = drive->id;
656 ide_hwif_t *hwif = HWIF(drive);
657 ide_dma_action_t dma_func = ide_dma_off_quietly;
658
659 if (id && (id->capability & 1) && hwif->autodma) {
660 /* Consult the list of known "bad" drives */
661 if (ide_dmaproc(ide_dma_bad_drive, drive)) {
662 dma_func = ide_dma_off;
663 goto fast_ata_pio;
664 }
665 dma_func = ide_dma_off_quietly;
666 if (id->field_valid & 4) {
667 if (id->dma_ultra & 0x002F) {
668 /* Force if Capable UltraDMA */
669 dma_func = config_chipset_for_dma(drive, 1);
670 if ((id->field_valid & 2) &&
671 (dma_func != ide_dma_on))
672 goto try_dma_modes;
673 }
674 } else if (id->field_valid & 2) {
675 try_dma_modes:
676 if ((id->dma_mword & 0x0007) ||
677 (id->dma_1word & 0x0007)) {
678 /* Force if Capable regular DMA modes */
679 dma_func = config_chipset_for_dma(drive, 0);
680 if (dma_func != ide_dma_on)
681 goto no_dma_set;
682 }
683 } else if (ide_dmaproc(ide_dma_good_drive, drive)) {
684 if (id->eide_dma_time > 150) {
685 goto no_dma_set;
686 }
687 /* Consult the list of known "good" drives */
688 dma_func = config_chipset_for_dma(drive, 0);
689 if (dma_func != ide_dma_on)
690 goto no_dma_set;
691 } else {
692 goto fast_ata_pio;
693 }
694 } else if ((id->capability & 8) || (id->field_valid & 2)) {
695 fast_ata_pio:
696 dma_func = ide_dma_off_quietly;
697 no_dma_set:
698 (void) config_chipset_for_pio(drive, 5);
699 }
700
701 return HWIF(drive)->dmaproc(dma_func, drive);
702 }
703
704 int pdc202xx_quirkproc (ide_drive_t *drive)
705 {
706 return ((int) check_in_drive_lists(drive, pdc_quirk_drives));
707 }
708
709 /*
710 * pdc202xx_dmaproc() initiates/aborts (U)DMA read/write operations on a drive.
711 */
712 int pdc202xx_dmaproc (ide_dma_action_t func, ide_drive_t *drive)
713 {
714 byte dma_stat = 0, sc1d = 0;
715 unsigned long high_16 = pci_resource_start(HWIF(drive)->pci_dev, 4);
716 unsigned long dma_base = HWIF(drive)->dma_base;
717
718 switch (func) {
719 case ide_dma_check:
720 return config_drive_xfer_rate(drive);
721 case ide_dma_test_irq: /* returns 1 if dma irq issued, 0 otherwise */
722 dma_stat = inb(dma_base+2);
723 sc1d = inb(high_16 + 0x001d);
724 if (HWIF(drive)->channel) {
725 if ((sc1d & 0x50) == 0x50) goto somebody_else;
726 else if ((sc1d & 0x40) == 0x40)
727 return (dma_stat & 4) == 4;
728 } else {
729 if ((sc1d & 0x05) == 0x05) goto somebody_else;
730 else if ((sc1d & 0x04) == 0x04)
731 return (dma_stat & 4) == 4;
732 }
733 somebody_else:
734 return (dma_stat & 4) == 4; /* return 1 if INTR asserted */
735 case ide_dma_lostirq:
736 case ide_dma_timeout:
737 if (HWIF(drive)->resetproc != NULL)
738 HWIF(drive)->resetproc(drive);
739 default:
740 break;
741 }
742 return ide_dmaproc(func, drive); /* use standard DMA stuff */
743 }
744 #endif /* CONFIG_BLK_DEV_IDEDMA */
745
746 void pdc202xx_reset (ide_drive_t *drive)
747 {
748 unsigned long high_16 = pci_resource_start(HWIF(drive)->pci_dev, 4);
749 byte udma_speed_flag = inb(high_16 + 0x001f);
750 int i = 0;
751
752 OUT_BYTE(udma_speed_flag | 0x10, high_16 + 0x001f);
753 ide_delay_50ms();
754 ide_delay_50ms();
755 OUT_BYTE(udma_speed_flag & ~0x10, high_16 + 0x001f);
756 for (i = 0; i < 40; i++)
757 ide_delay_50ms();
758 }
759
760 unsigned int __init pci_init_pdc202xx (struct pci_dev *dev, const char *name)
761 {
762 unsigned long high_16 = pci_resource_start(dev, 4);
763 byte udma_speed_flag = inb(high_16 + 0x001f);
764 byte primary_mode = inb(high_16 + 0x001a);
765 byte secondary_mode = inb(high_16 + 0x001b);
766
767 if ((dev->device == PCI_DEVICE_ID_PROMISE_20262) ||
768 (dev->device == PCI_DEVICE_ID_PROMISE_20265) ||
769 (dev->device == PCI_DEVICE_ID_PROMISE_20267)) {
770 int i = 0;
771 /*
772 * software reset - this is required because the bios
773 * will set UDMA timing on if the hdd supports it. The
774 * user may want to turn udma off. A bug in the pdc20262
775 * is that it cannot handle a downgrade in timing from UDMA
776 * to DMA. Disk accesses after issuing a set feature command
777 * will result in errors. A software reset leaves the timing
778 * registers intact, but resets the drives.
779 */
780
781 OUT_BYTE(udma_speed_flag | 0x10, high_16 + 0x001f);
782 ide_delay_50ms();
783 ide_delay_50ms();
784 OUT_BYTE(udma_speed_flag & ~0x10, high_16 + 0x001f);
785 for (i=0; i<40; i++)
786 ide_delay_50ms();
787 }
788
789 if (dev->resource[PCI_ROM_RESOURCE].start) {
790 pci_write_config_dword(dev, PCI_ROM_ADDRESS, dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
791 printk("%s: ROM enabled at 0x%08lx\n", name, dev->resource[PCI_ROM_RESOURCE].start);
792 }
793
794 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
795 byte irq = 0, irq2 = 0;
796 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
797 pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2); /* 0xbc */
798 if ((irq != irq2) && (dev->device != PCI_DEVICE_ID_PROMISE_20265) && (dev->device != PCI_DEVICE_ID_PROMISE_20267)) {
799 pci_write_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, irq); /* 0xbc */
800 printk("%s: pci-config space interrupt mirror fixed.\n", name);
801 }
802 }
803
804 printk("%s: (U)DMA Burst Bit %sABLED " \
805 "Primary %s Mode " \
806 "Secondary %s Mode.\n",
807 name,
808 (udma_speed_flag & 1) ? "EN" : "DIS",
809 (primary_mode & 1) ? "MASTER" : "PCI",
810 (secondary_mode & 1) ? "MASTER" : "PCI" );
811
812 #ifdef CONFIG_PDC202XX_BURST
813 if (!(udma_speed_flag & 1)) {
814 printk("%s: FORCING BURST BIT 0x%02x -> 0x%02x ", name, udma_speed_flag, (udma_speed_flag|1));
815 outb(udma_speed_flag|1, high_16 + 0x001f);
816 printk("%sCTIVE\n", (inb(high_16 + 0x001f) & 1) ? "A" : "INA");
817 }
818 #endif /* CONFIG_PDC202XX_BURST */
819
820 #ifdef CONFIG_PDC202XX_MASTER
821 if (!(primary_mode & 1)) {
822 printk("%s: FORCING PRIMARY MODE BIT 0x%02x -> 0x%02x ",
823 name, primary_mode, (primary_mode|1));
824 outb(primary_mode|1, high_16 + 0x001a);
825 printk("%s\n", (inb(high_16 + 0x001a) & 1) ? "MASTER" : "PCI");
826 }
827
828 if (!(secondary_mode & 1)) {
829 printk("%s: FORCING SECONDARY MODE BIT 0x%02x -> 0x%02x ",
830 name, secondary_mode, (secondary_mode|1));
831 outb(secondary_mode|1, high_16 + 0x001b);
832 printk("%s\n", (inb(high_16 + 0x001b) & 1) ? "MASTER" : "PCI");
833 }
834 #endif /* CONFIG_PDC202XX_MASTER */
835
836 #if defined(DISPLAY_PDC202XX_TIMINGS) && defined(CONFIG_PROC_FS)
837 if (!pdc202xx_proc) {
838 pdc202xx_proc = 1;
839 bmide_dev = dev;
840 pdc202xx_display_info = &pdc202xx_get_info;
841 }
842 #endif /* DISPLAY_PDC202XX_TIMINGS && CONFIG_PROC_FS */
843 return dev->irq;
844 }
845
846 unsigned int __init ata66_pdc202xx (ide_hwif_t *hwif)
847 {
848 unsigned short mask = (hwif->channel) ? (1<<11) : (1<<10);
849 unsigned short CIS;
850
851 pci_read_config_word(hwif->pci_dev, 0x50, &CIS);
852 return ((CIS & mask) ? 0 : 1);
853 }
854
855 void __init ide_init_pdc202xx (ide_hwif_t *hwif)
856 {
857 hwif->tuneproc = &pdc202xx_tune_drive;
858 hwif->speedproc = &pdc202xx_tune_chipset;
859 hwif->quirkproc = &pdc202xx_quirkproc;
860
861 if ((hwif->pci_dev->device == PCI_DEVICE_ID_PROMISE_20262) ||
862 (hwif->pci_dev->device == PCI_DEVICE_ID_PROMISE_20265) ||
863 (hwif->pci_dev->device == PCI_DEVICE_ID_PROMISE_20267)) {
864 hwif->resetproc = &pdc202xx_reset;
865 }
866
867 #ifdef CONFIG_BLK_DEV_IDEDMA
868 if (hwif->dma_base) {
869 hwif->dmaproc = &pdc202xx_dmaproc;
870 hwif->autodma = 1;
871 } else {
872 hwif->drives[0].autotune = 1;
873 hwif->drives[1].autotune = 1;
874 hwif->autodma = 0;
875 }
876 #else /* !CONFIG_BLK_DEV_IDEDMA */
877 hwif->drives[0].autotune = 1;
878 hwif->drives[1].autotune = 1;
879 hwif->autodma = 0;
880 #endif /* CONFIG_BLK_DEV_IDEDMA */
881 }
882
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