1 /*
2 * linux/drivers/ide/ide-pci.c Version 1.05 June 9, 2000
3 *
4 * Copyright (c) 1998-2000 Andre Hedrick <andre@linux-ide.org>
5 *
6 * Copyright (c) 1995-1998 Mark Lord
7 * May be copied or modified under the terms of the GNU General Public License
8 */
9
10 /*
11 * This module provides support for automatic detection and
12 * configuration of all PCI IDE interfaces present in a system.
13 */
14
15 #include <linux/config.h>
16 #include <linux/types.h>
17 #include <linux/kernel.h>
18 #include <linux/timer.h>
19 #include <linux/mm.h>
20 #include <linux/interrupt.h>
21 #include <linux/pci.h>
22 #include <linux/init.h>
23 #include <linux/ide.h>
24
25 #include <asm/io.h>
26 #include <asm/irq.h>
27
28 #define DEVID_PIIXa ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371FB_0})
29 #define DEVID_PIIXb ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371FB_1})
30 #define DEVID_PIIX3 ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_1})
31 #define DEVID_PIIX4 ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB})
32 #define DEVID_PIIX4E ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_1})
33 #define DEVID_PIIX4E2 ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_1})
34 #define DEVID_PIIX4U ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_1})
35 #define DEVID_PIIX4U2 ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82372FB_1})
36 #define DEVID_PIIX4NX ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX})
37 #define DEVID_PIIX4U3 ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82820FW_5})
38 #define DEVID_VIA_IDE ((ide_pci_devid_t){PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C561})
39 #define DEVID_VP_IDE ((ide_pci_devid_t){PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1})
40 #define DEVID_PDC20246 ((ide_pci_devid_t){PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20246})
41 #define DEVID_PDC20262 ((ide_pci_devid_t){PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20262})
42 #define DEVID_PDC20265 ((ide_pci_devid_t){PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20265})
43 #define DEVID_PDC20267 ((ide_pci_devid_t){PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20267})
44 #define DEVID_RZ1000 ((ide_pci_devid_t){PCI_VENDOR_ID_PCTECH, PCI_DEVICE_ID_PCTECH_RZ1000})
45 #define DEVID_RZ1001 ((ide_pci_devid_t){PCI_VENDOR_ID_PCTECH, PCI_DEVICE_ID_PCTECH_RZ1001})
46 #define DEVID_SAMURAI ((ide_pci_devid_t){PCI_VENDOR_ID_PCTECH, PCI_DEVICE_ID_PCTECH_SAMURAI_IDE})
47 #define DEVID_CMD640 ((ide_pci_devid_t){PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_640})
48 #define DEVID_CMD643 ((ide_pci_devid_t){PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_643})
49 #define DEVID_CMD646 ((ide_pci_devid_t){PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_646})
50 #define DEVID_CMD648 ((ide_pci_devid_t){PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_648})
51 #define DEVID_CMD649 ((ide_pci_devid_t){PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_649})
52 #define DEVID_SIS5513 ((ide_pci_devid_t){PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5513})
53 #define DEVID_OPTI621 ((ide_pci_devid_t){PCI_VENDOR_ID_OPTI, PCI_DEVICE_ID_OPTI_82C621})
54 #define DEVID_OPTI621V ((ide_pci_devid_t){PCI_VENDOR_ID_OPTI, PCI_DEVICE_ID_OPTI_82C558})
55 #define DEVID_OPTI621X ((ide_pci_devid_t){PCI_VENDOR_ID_OPTI, PCI_DEVICE_ID_OPTI_82C825})
56 #define DEVID_TRM290 ((ide_pci_devid_t){PCI_VENDOR_ID_TEKRAM, PCI_DEVICE_ID_TEKRAM_DC290})
57 #define DEVID_NS87410 ((ide_pci_devid_t){PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_87410})
58 #define DEVID_NS87415 ((ide_pci_devid_t){PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_87415})
59 #define DEVID_HT6565 ((ide_pci_devid_t){PCI_VENDOR_ID_HOLTEK, PCI_DEVICE_ID_HOLTEK_6565})
60 #define DEVID_AEC6210 ((ide_pci_devid_t){PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP850UF})
61 #define DEVID_AEC6260 ((ide_pci_devid_t){PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP860})
62 #define DEVID_AEC6260R ((ide_pci_devid_t){PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP860R})
63 #define DEVID_W82C105 ((ide_pci_devid_t){PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105})
64 #define DEVID_UM8673F ((ide_pci_devid_t){PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8673F})
65 #define DEVID_UM8886A ((ide_pci_devid_t){PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886A})
66 #define DEVID_UM8886BF ((ide_pci_devid_t){PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886BF})
67 #define DEVID_HPT34X ((ide_pci_devid_t){PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT343})
68 #define DEVID_HPT366 ((ide_pci_devid_t){PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT366})
69 #define DEVID_ALI15X3 ((ide_pci_devid_t){PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M5229})
70 #define DEVID_CY82C693 ((ide_pci_devid_t){PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693})
71 #define DEVID_HINT ((ide_pci_devid_t){0x3388, 0x8013})
72 #define DEVID_CS5530 ((ide_pci_devid_t){PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_IDE})
73 #define DEVID_AMD7403 ((ide_pci_devid_t){PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_COBRA_7403})
74 #define DEVID_AMD7409 ((ide_pci_devid_t){PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7409})
75 #define DEVID_SLC90E66 ((ide_pci_devid_t){PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1})
76 #define DEVID_OSB4 ((ide_pci_devid_t){PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE})
77
78 #define IDE_IGNORE ((void *)-1)
79
80 #ifdef CONFIG_BLK_DEV_AEC62XX
81 extern unsigned int pci_init_aec62xx(struct pci_dev *, const char *);
82 extern unsigned int ata66_aec62xx(ide_hwif_t *);
83 extern void ide_init_aec62xx(ide_hwif_t *);
84 extern void ide_dmacapable_aec62xx(ide_hwif_t *, unsigned long);
85 #define PCI_AEC62XX &pci_init_aec62xx
86 #define ATA66_AEC62XX &ata66_aec62xx
87 #define INIT_AEC62XX &ide_init_aec62xx
88 #define DMA_AEC62XX &ide_dmacapable_aec62xx
89 #else
90 #define PCI_AEC62XX NULL
91 #define ATA66_AEC62XX NULL
92 #define INIT_AEC62XX NULL
93 #define DMA_AEC62XX NULL
94 #endif
95
96 #ifdef CONFIG_BLK_DEV_ALI15X3
97 extern unsigned int pci_init_ali15x3(struct pci_dev *, const char *);
98 extern unsigned int ata66_ali15x3(ide_hwif_t *);
99 extern void ide_init_ali15x3(ide_hwif_t *);
100 extern void ide_dmacapable_ali15x3(ide_hwif_t *, unsigned long);
101 #define PCI_ALI15X3 &pci_init_ali15x3
102 #define ATA66_ALI15X3 &ata66_ali15x3
103 #define INIT_ALI15X3 &ide_init_ali15x3
104 #define DMA_ALI15X3 &ide_dmacapable_ali15x3
105 #else
106 #define PCI_ALI15X3 NULL
107 #define ATA66_ALI15X3 NULL
108 #define INIT_ALI15X3 NULL
109 #define DMA_ALI15X3 NULL
110 #endif
111
112 #ifdef CONFIG_BLK_DEV_AMD7409
113 extern unsigned int pci_init_amd7409(struct pci_dev *, const char *);
114 extern unsigned int ata66_amd7409(ide_hwif_t *);
115 extern void ide_init_amd7409(ide_hwif_t *);
116 extern void ide_dmacapable_amd7409(ide_hwif_t *, unsigned long);
117 #define PCI_AMD7409 &pci_init_amd7409
118 #define ATA66_AMD7409 &ata66_amd7409
119 #define INIT_AMD7409 &ide_init_amd7409
120 #define DMA_AMD7409 &ide_dmacapable_amd7409
121 #else
122 #define PCI_AMD7409 NULL
123 #define ATA66_AMD7409 NULL
124 #define INIT_AMD7409 NULL
125 #define DMA_AMD7409 NULL
126 #endif
127
128 #ifdef CONFIG_BLK_DEV_CMD64X
129 extern unsigned int pci_init_cmd64x(struct pci_dev *, const char *);
130 extern unsigned int ata66_cmd64x(ide_hwif_t *);
131 extern void ide_init_cmd64x(ide_hwif_t *);
132 extern void ide_dmacapable_cmd64x(ide_hwif_t *, unsigned long);
133 #define PCI_CMD64X &pci_init_cmd64x
134 #define ATA66_CMD64X &ata66_cmd64x
135 #define INIT_CMD64X &ide_init_cmd64x
136 #else
137 #define PCI_CMD64X NULL
138 #define ATA66_CMD64X NULL
139 #ifdef __sparc_v9__
140 #define INIT_CMD64X IDE_IGNORE
141 #else
142 #define INIT_CMD64X NULL
143 #endif
144 #endif
145
146 #ifdef CONFIG_BLK_DEV_CY82C693
147 extern unsigned int pci_init_cy82c693(struct pci_dev *, const char *);
148 extern void ide_init_cy82c693(ide_hwif_t *);
149 #define PCI_CY82C693 &pci_init_cy82c693
150 #define INIT_CY82C693 &ide_init_cy82c693
151 #else
152 #define PCI_CY82C693 NULL
153 #define INIT_CY82C693 NULL
154 #endif
155
156 #ifdef CONFIG_BLK_DEV_CS5530
157 extern unsigned int pci_init_cs5530(struct pci_dev *, const char *);
158 extern void ide_init_cs5530(ide_hwif_t *);
159 #define PCI_CS5530 &pci_init_cs5530
160 #define INIT_CS5530 &ide_init_cs5530
161 #else
162 #define PCI_CS5530 NULL
163 #define INIT_CS5530 NULL
164 #endif
165
166 #ifdef CONFIG_BLK_DEV_HPT34X
167 extern unsigned int pci_init_hpt34x(struct pci_dev *, const char *);
168 extern void ide_init_hpt34x(ide_hwif_t *);
169 #define PCI_HPT34X &pci_init_hpt34x
170 #define INIT_HPT34X &ide_init_hpt34x
171 #else
172 #define PCI_HPT34X NULL
173 #define INIT_HPT34X IDE_IGNORE
174 #endif
175
176 #ifdef CONFIG_BLK_DEV_HPT366
177 extern byte hpt363_shared_irq;
178 extern byte hpt363_shared_pin;
179 extern unsigned int pci_init_hpt366(struct pci_dev *, const char *);
180 extern unsigned int ata66_hpt366(ide_hwif_t *);
181 extern void ide_init_hpt366(ide_hwif_t *);
182 extern void ide_dmacapable_hpt366(ide_hwif_t *, unsigned long);
183 #define PCI_HPT366 &pci_init_hpt366
184 #define ATA66_HPT366 &ata66_hpt366
185 #define INIT_HPT366 &ide_init_hpt366
186 #define DMA_HPT366 &ide_dmacapable_hpt366
187 #else
188 static byte hpt363_shared_irq = 0;
189 static byte hpt363_shared_pin = 0;
190 #define PCI_HPT366 NULL
191 #define ATA66_HPT366 NULL
192 #define INIT_HPT366 NULL
193 #define DMA_HPT366 NULL
194 #endif
195
196 #ifdef CONFIG_BLK_DEV_NS87415
197 extern void ide_init_ns87415(ide_hwif_t *);
198 #define INIT_NS87415 &ide_init_ns87415
199 #else
200 #define INIT_NS87415 IDE_IGNORE
201 #endif
202
203 #ifdef CONFIG_BLK_DEV_OPTI621
204 extern void ide_init_opti621(ide_hwif_t *);
205 #define INIT_OPTI621 &ide_init_opti621
206 #else
207 #define INIT_OPTI621 NULL
208 #endif
209
210 #ifdef CONFIG_BLK_DEV_OSB4
211 extern unsigned int pci_init_osb4(struct pci_dev *, const char *);
212 extern unsigned int ata66_osb4(ide_hwif_t *);
213 extern void ide_init_osb4(ide_hwif_t *);
214 #define PCI_OSB4 &pci_init_osb4
215 #define ATA66_OSB4 &ata66_osb4
216 #define INIT_OSB4 &ide_init_osb4
217 #else
218 #define PCI_OSB4 NULL
219 #define ATA66_OSB4 NULL
220 #define INIT_OSB4 NULL
221 #endif
222
223 #ifdef CONFIG_BLK_DEV_PDC202XX
224 extern unsigned int pci_init_pdc202xx(struct pci_dev *, const char *);
225 extern unsigned int ata66_pdc202xx(ide_hwif_t *);
226 extern void ide_init_pdc202xx(ide_hwif_t *);
227 #define PCI_PDC202XX &pci_init_pdc202xx
228 #define ATA66_PDC202XX &ata66_pdc202xx
229 #define INIT_PDC202XX &ide_init_pdc202xx
230 #else
231 #define PCI_PDC202XX NULL
232 #define ATA66_PDC202XX NULL
233 #define INIT_PDC202XX NULL
234 #endif
235
236 #ifdef CONFIG_BLK_DEV_PIIX
237 extern unsigned int pci_init_piix(struct pci_dev *, const char *);
238 extern unsigned int ata66_piix(ide_hwif_t *);
239 extern void ide_init_piix(ide_hwif_t *);
240 #define PCI_PIIX &pci_init_piix
241 #define ATA66_PIIX &ata66_piix
242 #define INIT_PIIX &ide_init_piix
243 #else
244 #define PCI_PIIX NULL
245 #define ATA66_PIIX NULL
246 #define INIT_PIIX NULL
247 #endif
248
249 #ifdef CONFIG_BLK_DEV_RZ1000
250 extern void ide_init_rz1000(ide_hwif_t *);
251 #define INIT_RZ1000 &ide_init_rz1000
252 #else
253 #define INIT_RZ1000 IDE_IGNORE
254 #endif
255
256 #define INIT_SAMURAI NULL
257
258 #ifdef CONFIG_BLK_DEV_SIS5513
259 extern unsigned int pci_init_sis5513(struct pci_dev *, const char *);
260 extern unsigned int ata66_sis5513(ide_hwif_t *);
261 extern void ide_init_sis5513(ide_hwif_t *);
262 #define PCI_SIS5513 &pci_init_sis5513
263 #define ATA66_SIS5513 &ata66_sis5513
264 #define INIT_SIS5513 &ide_init_sis5513
265 #else
266 #define PCI_SIS5513 NULL
267 #define ATA66_SIS5513 NULL
268 #define INIT_SIS5513 NULL
269 #endif
270
271 #ifdef CONFIG_BLK_DEV_SLC90E66
272 extern unsigned int pci_init_slc90e66(struct pci_dev *, const char *);
273 extern unsigned int ata66_slc90e66(ide_hwif_t *);
274 extern void ide_init_slc90e66(ide_hwif_t *);
275 #define PCI_SLC90E66 &pci_init_slc90e66
276 #define ATA66_SLC90E66 &ata66_slc90e66
277 #define INIT_SLC90E66 &ide_init_slc90e66
278 #else
279 #define PCI_SLC90E66 NULL
280 #define ATA66_SLC90E66 NULL
281 #define INIT_SLC90E66 NULL
282 #endif
283
284 #ifdef CONFIG_BLK_DEV_SL82C105
285 extern void ide_init_sl82c105(ide_hwif_t *);
286 extern void ide_dmacapable_sl82c105(ide_hwif_t *, unsigned long);
287 #define INIT_W82C105 &ide_init_sl82c105
288 #define DMA_W82C105 &ide_dmacapable_sl82c105
289 #else
290 #define INIT_W82C105 IDE_IGNORE
291 #define DMA_W82C105 NULL
292 #endif
293
294 #ifdef CONFIG_BLK_DEV_TRM290
295 extern void ide_init_trm290(ide_hwif_t *);
296 #define INIT_TRM290 &ide_init_trm290
297 #else
298 #define INIT_TRM290 IDE_IGNORE
299 #endif
300
301 #ifdef CONFIG_BLK_DEV_VIA82CXXX
302 extern unsigned int pci_init_via82cxxx(struct pci_dev *, const char *);
303 extern unsigned int ata66_via82cxxx(ide_hwif_t *);
304 extern void ide_init_via82cxxx(ide_hwif_t *);
305 extern void ide_dmacapable_via82cxxx(ide_hwif_t *, unsigned long);
306 #define PCI_VIA82CXXX &pci_init_via82cxxx
307 #define ATA66_VIA82CXXX &ata66_via82cxxx
308 #define INIT_VIA82CXXX &ide_init_via82cxxx
309 #define DMA_VIA82CXXX &ide_dmacapable_via82cxxx
310 #else
311 #define PCI_VIA82CXXX NULL
312 #define ATA66_VIA82CXXX NULL
313 #define INIT_VIA82CXXX NULL
314 #define DMA_VIA82CXXX NULL
315 #endif
316
317 typedef struct ide_pci_enablebit_s {
318 byte reg; /* byte pci reg holding the enable-bit */
319 byte mask; /* mask to isolate the enable-bit */
320 byte val; /* value of masked reg when "enabled" */
321 } ide_pci_enablebit_t;
322
323 typedef struct ide_pci_device_s {
324 ide_pci_devid_t devid;
325 char *name;
326 unsigned int (*init_chipset)(struct pci_dev *dev, const char *name);
327 unsigned int (*ata66_check)(ide_hwif_t *hwif);
328 void (*init_hwif)(ide_hwif_t *hwif);
329 void (*dma_init)(ide_hwif_t *hwif, unsigned long dmabase);
330 ide_pci_enablebit_t enablebits[2];
331 byte bootable;
332 unsigned int extra;
333 } ide_pci_device_t;
334
335 static ide_pci_device_t ide_pci_chipsets[] __initdata = {
336 {DEVID_PIIXa, "PIIX", NULL, NULL, INIT_PIIX, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 },
337 {DEVID_PIIXb, "PIIX", NULL, NULL, INIT_PIIX, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 },
338 {DEVID_PIIX3, "PIIX3", PCI_PIIX, NULL, INIT_PIIX, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 },
339 {DEVID_PIIX4, "PIIX4", PCI_PIIX, NULL, INIT_PIIX, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 },
340 {DEVID_PIIX4E, "PIIX4", PCI_PIIX, NULL, INIT_PIIX, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 },
341 {DEVID_PIIX4E2, "PIIX4", PCI_PIIX, NULL, INIT_PIIX, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 },
342 {DEVID_PIIX4U, "PIIX4", PCI_PIIX, ATA66_PIIX, INIT_PIIX, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 },
343 {DEVID_PIIX4U2, "PIIX4", PCI_PIIX, ATA66_PIIX, INIT_PIIX, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 },
344 {DEVID_PIIX4NX, "PIIX4", PCI_PIIX, NULL, INIT_PIIX, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 },
345 {DEVID_PIIX4U3, "PIIX4", PCI_PIIX, ATA66_PIIX, INIT_PIIX, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 },
346 {DEVID_VIA_IDE, "VIA_IDE", NULL, NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
347 {DEVID_VP_IDE, "VP_IDE", PCI_VIA82CXXX, ATA66_VIA82CXXX,INIT_VIA82CXXX, DMA_VIA82CXXX, {{0x40,0x02,0x02}, {0x40,0x01,0x01}}, ON_BOARD, 0 },
348 {DEVID_PDC20246,"PDC20246", PCI_PDC202XX, NULL, INIT_PDC202XX, NULL, {{0x50,0x02,0x02}, {0x50,0x04,0x04}}, OFF_BOARD, 16 },
349 {DEVID_PDC20262,"PDC20262", PCI_PDC202XX, ATA66_PDC202XX, INIT_PDC202XX, NULL, {{0x50,0x02,0x02}, {0x50,0x04,0x04}}, OFF_BOARD, 48 },
350 {DEVID_PDC20265,"PDC20265", PCI_PDC202XX, ATA66_PDC202XX, INIT_PDC202XX, NULL, {{0x50,0x02,0x02}, {0x50,0x04,0x04}}, OFF_BOARD, 48 },
351 {DEVID_PDC20267,"PDC20267", PCI_PDC202XX, ATA66_PDC202XX, INIT_PDC202XX, NULL, {{0x50,0x02,0x02}, {0x50,0x04,0x04}}, OFF_BOARD, 48 },
352 {DEVID_RZ1000, "RZ1000", NULL, NULL, INIT_RZ1000, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
353 {DEVID_RZ1001, "RZ1001", NULL, NULL, INIT_RZ1000, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
354 {DEVID_SAMURAI, "SAMURAI", NULL, NULL, INIT_SAMURAI, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
355 {DEVID_CMD640, "CMD640", NULL, NULL, IDE_IGNORE, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
356 {DEVID_NS87410, "NS87410", NULL, NULL, NULL, NULL, {{0x43,0x08,0x08}, {0x47,0x08,0x08}}, ON_BOARD, 0 },
357 {DEVID_SIS5513, "SIS5513", PCI_SIS5513, ATA66_SIS5513, INIT_SIS5513, NULL, {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}}, ON_BOARD, 0 },
358 {DEVID_CMD643, "CMD643", PCI_CMD64X, NULL, INIT_CMD64X, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
359 {DEVID_CMD646, "CMD646", PCI_CMD64X, NULL, INIT_CMD64X, NULL, {{0x00,0x00,0x00}, {0x51,0x80,0x80}}, ON_BOARD, 0 },
360 {DEVID_CMD648, "CMD648", PCI_CMD64X, ATA66_CMD64X, INIT_CMD64X, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
361 {DEVID_CMD649, "CMD649", PCI_CMD64X, ATA66_CMD64X, INIT_CMD64X, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
362 {DEVID_HT6565, "HT6565", NULL, NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
363 {DEVID_OPTI621, "OPTI621", NULL, NULL, INIT_OPTI621, NULL, {{0x45,0x80,0x00}, {0x40,0x08,0x00}}, ON_BOARD, 0 },
364 {DEVID_OPTI621X,"OPTI621X", NULL, NULL, INIT_OPTI621, NULL, {{0x45,0x80,0x00}, {0x40,0x08,0x00}}, ON_BOARD, 0 },
365 {DEVID_TRM290, "TRM290", NULL, NULL, INIT_TRM290, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
366 {DEVID_NS87415, "NS87415", NULL, NULL, INIT_NS87415, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
367 {DEVID_AEC6210, "AEC6210", PCI_AEC62XX, NULL, INIT_AEC62XX, DMA_AEC62XX, {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}}, OFF_BOARD, 0 },
368 {DEVID_AEC6260, "AEC6260", PCI_AEC62XX, ATA66_AEC62XX, INIT_AEC62XX, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, NEVER_BOARD, 0 },
369 {DEVID_AEC6260R,"AEC6260R", PCI_AEC62XX, ATA66_AEC62XX, INIT_AEC62XX, NULL, {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}}, OFF_BOARD, 0 },
370 {DEVID_W82C105, "W82C105", NULL, NULL, INIT_W82C105, DMA_W82C105, {{0x40,0x01,0x01}, {0x40,0x10,0x10}}, ON_BOARD, 0 },
371 {DEVID_UM8673F, "UM8673F", NULL, NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
372 {DEVID_UM8886A, "UM8886A", NULL, NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
373 {DEVID_UM8886BF,"UM8886BF", NULL, NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
374 {DEVID_HPT34X, "HPT34X", PCI_HPT34X, NULL, INIT_HPT34X, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, NEVER_BOARD, 16 },
375 {DEVID_HPT366, "HPT366", PCI_HPT366, ATA66_HPT366, INIT_HPT366, DMA_HPT366, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, OFF_BOARD, 240 },
376 {DEVID_ALI15X3, "ALI15X3", PCI_ALI15X3, ATA66_ALI15X3, INIT_ALI15X3, DMA_ALI15X3, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
377 {DEVID_CY82C693,"CY82C693", PCI_CY82C693, NULL, INIT_CY82C693, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
378 {DEVID_HINT, "HINT_IDE", NULL, NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
379 {DEVID_CS5530, "CS5530", PCI_CS5530, NULL, INIT_CS5530, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
380 {DEVID_AMD7403, "AMD7403", NULL, NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
381 {DEVID_AMD7409, "AMD7409", PCI_AMD7409, ATA66_AMD7409, INIT_AMD7409, DMA_AMD7409, {{0x40,0x01,0x01}, {0x40,0x02,0x02}}, ON_BOARD, 0 },
382 {DEVID_SLC90E66,"SLC90E66", PCI_SLC90E66, ATA66_SLC90E66, INIT_SLC90E66, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 },
383 {DEVID_OSB4, "ServerWorks OSB4", PCI_OSB4, ATA66_OSB4, INIT_OSB4, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 },
384 {IDE_PCI_DEVID_NULL, "PCI_IDE", NULL, NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 }};
385
386 /*
387 * This allows offboard ide-pci cards the enable a BIOS, verify interrupt
388 * settings of split-mirror pci-config space, place chipset into init-mode,
389 * and/or preserve an interrupt if the card is not native ide support.
390 */
391 static unsigned int __init ide_special_settings (struct pci_dev *dev, const char *name)
392 {
393 switch(dev->device) {
394 case PCI_DEVICE_ID_TTI_HPT366:
395 case PCI_DEVICE_ID_PROMISE_20246:
396 case PCI_DEVICE_ID_PROMISE_20262:
397 case PCI_DEVICE_ID_PROMISE_20265:
398 case PCI_DEVICE_ID_PROMISE_20267:
399 case PCI_DEVICE_ID_ARTOP_ATP850UF:
400 case PCI_DEVICE_ID_ARTOP_ATP860:
401 case PCI_DEVICE_ID_ARTOP_ATP860R:
402 return dev->irq;
403 default:
404 break;
405 }
406 return 0;
407 }
408
409 /*
410 * Match a PCI IDE port against an entry in ide_hwifs[],
411 * based on io_base port if possible.
412 */
413 static ide_hwif_t __init *ide_match_hwif (unsigned long io_base, byte bootable, const char *name)
414 {
415 int h;
416 ide_hwif_t *hwif;
417
418 /*
419 * Look for a hwif with matching io_base specified using
420 * parameters to ide_setup().
421 */
422 for (h = 0; h < MAX_HWIFS; ++h) {
423 hwif = &ide_hwifs[h];
424 if (hwif->io_ports[IDE_DATA_OFFSET] == io_base) {
425 if (hwif->chipset == ide_generic)
426 return hwif; /* a perfect match */
427 }
428 }
429 /*
430 * Look for a hwif with matching io_base default value.
431 * If chipset is "ide_unknown", then claim that hwif slot.
432 * Otherwise, some other chipset has already claimed it.. :(
433 */
434 for (h = 0; h < MAX_HWIFS; ++h) {
435 hwif = &ide_hwifs[h];
436 if (hwif->io_ports[IDE_DATA_OFFSET] == io_base) {
437 if (hwif->chipset == ide_unknown)
438 return hwif; /* match */
439 printk("%s: port 0x%04lx already claimed by %s\n", name, io_base, hwif->name);
440 return NULL; /* already claimed */
441 }
442 }
443 /*
444 * Okay, there is no hwif matching our io_base,
445 * so we'll just claim an unassigned slot.
446 * Give preference to claiming other slots before claiming ide0/ide1,
447 * just in case there's another interface yet-to-be-scanned
448 * which uses ports 1f0/170 (the ide0/ide1 defaults).
449 *
450 * Unless there is a bootable card that does not use the standard
451 * ports 1f0/170 (the ide0/ide1 defaults). The (bootable) flag.
452 */
453 if (bootable) {
454 for (h = 0; h < MAX_HWIFS; ++h) {
455 hwif = &ide_hwifs[h];
456 if (hwif->chipset == ide_unknown)
457 return hwif; /* pick an unused entry */
458 }
459 } else {
460 for (h = 2; h < MAX_HWIFS; ++h) {
461 hwif = ide_hwifs + h;
462 if (hwif->chipset == ide_unknown)
463 return hwif; /* pick an unused entry */
464 }
465 }
466 for (h = 0; h < 2; ++h) {
467 hwif = ide_hwifs + h;
468 if (hwif->chipset == ide_unknown)
469 return hwif; /* pick an unused entry */
470 }
471 printk("%s: too many IDE interfaces, no room in table\n", name);
472 return NULL;
473 }
474
475 static int __init ide_setup_pci_baseregs (struct pci_dev *dev, const char *name)
476 {
477 byte reg, progif = 0;
478
479 /*
480 * Place both IDE interfaces into PCI "native" mode:
481 */
482 if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) || (progif & 5) != 5) {
483 if ((progif & 0xa) != 0xa) {
484 printk("%s: device not capable of full native PCI mode\n", name);
485 return 1;
486 }
487 printk("%s: placing both ports into native PCI mode\n", name);
488 (void) pci_write_config_byte(dev, PCI_CLASS_PROG, progif|5);
489 if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) || (progif & 5) != 5) {
490 printk("%s: rewrite of PROGIF failed, wanted 0x%04x, got 0x%04x\n", name, progif|5, progif);
491 return 1;
492 }
493 }
494 /*
495 * Setup base registers for IDE command/control spaces for each interface:
496 */
497 for (reg = 0; reg < 4; reg++) {
498 struct resource *res = dev->resource + reg;
499 if ((res->flags & IORESOURCE_IO) == 0)
500 continue;
501 if (!res->start) {
502 printk("%s: Missing I/O address #%d\n", name, reg);
503 return 1;
504 }
505 }
506 return 0;
507 }
508
509 /*
510 * ide_setup_pci_device() looks at the primary/secondary interfaces
511 * on a PCI IDE device and, if they are enabled, prepares the IDE driver
512 * for use with them. This generic code works for most PCI chipsets.
513 *
514 * One thing that is not standardized is the location of the
515 * primary/secondary interface "enable/disable" bits. For chipsets that
516 * we "know" about, this information is in the ide_pci_device_t struct;
517 * for all other chipsets, we just assume both interfaces are enabled.
518 */
519 static void __init ide_setup_pci_device (struct pci_dev *dev, ide_pci_device_t *d)
520 {
521 unsigned int port, at_least_one_hwif_enabled = 0, autodma = 0, pciirq = 0;
522 unsigned short pcicmd = 0, tried_config = 0;
523 byte tmp = 0;
524 ide_hwif_t *hwif, *mate = NULL;
525 unsigned int class_rev;
526
527 #ifdef CONFIG_IDEDMA_AUTO
528 autodma = 1;
529 #endif
530
531 pci_enable_device(dev);
532
533 check_if_enabled:
534 if (pci_read_config_word(dev, PCI_COMMAND, &pcicmd)) {
535 printk("%s: error accessing PCI regs\n", d->name);
536 return;
537 }
538 if (!(pcicmd & PCI_COMMAND_IO)) { /* is device disabled? */
539 /*
540 * PnP BIOS was *supposed* to have set this device up for us,
541 * but we can do it ourselves, so long as the BIOS has assigned an IRQ
542 * (or possibly the device is using a "legacy header" for IRQs).
543 * Maybe the user deliberately *disabled* the device,
544 * but we'll eventually ignore it again if no drives respond.
545 */
546 if (tried_config++
547 || ide_setup_pci_baseregs(dev, d->name)
548 || pci_write_config_word(dev, PCI_COMMAND, pcicmd | PCI_COMMAND_IO)) {
549 printk("%s: device disabled (BIOS)\n", d->name);
550 return;
551 }
552 autodma = 0; /* default DMA off if we had to configure it here */
553 goto check_if_enabled;
554 }
555 if (tried_config)
556 printk("%s: device enabled (Linux)\n", d->name);
557
558 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
559 class_rev &= 0xff;
560
561 if (IDE_PCI_DEVID_EQ(d->devid, DEVID_HPT34X)) {
562 /* see comments in hpt34x.c on why..... */
563 char *chipset_names[] = {"HPT343", "HPT345"};
564 strcpy(d->name, chipset_names[(pcicmd & PCI_COMMAND_MEMORY) ? 1 : 0]);
565 d->bootable = (pcicmd & PCI_COMMAND_MEMORY) ? OFF_BOARD : NEVER_BOARD;
566 }
567
568 printk("%s: chipset revision %d\n", d->name, class_rev);
569
570 /*
571 * Can we trust the reported IRQ?
572 */
573 pciirq = dev->irq;
574 if ((dev->class & ~(0xfa)) != ((PCI_CLASS_STORAGE_IDE << 8) | 5)) {
575 printk("%s: not 100%% native mode: will probe irqs later\n", d->name);
576 /*
577 * This allows offboard ide-pci cards the enable a BIOS,
578 * verify interrupt settings of split-mirror pci-config
579 * space, place chipset into init-mode, and/or preserve
580 * an interrupt if the card is not native ide support.
581 */
582 pciirq = (d->init_chipset) ? d->init_chipset(dev, d->name) : ide_special_settings(dev, d->name);
583 } else if (tried_config) {
584 printk("%s: will probe irqs later\n", d->name);
585 pciirq = 0;
586 } else if (!pciirq) {
587 printk("%s: bad irq (%d): will probe later\n", d->name, pciirq);
588 pciirq = 0;
589 } else {
590 if (d->init_chipset)
591 (void) d->init_chipset(dev, d->name);
592 #ifdef __sparc__
593 printk("%s: 100%% native mode on irq %s\n",
594 d->name, __irq_itoa(pciirq));
595 #else
596 printk("%s: 100%% native mode on irq %d\n", d->name, pciirq);
597 #endif
598 }
599
600 /*
601 * Set up the IDE ports
602 */
603 for (port = 0; port <= 1; ++port) {
604 unsigned long base = 0, ctl = 0;
605 ide_pci_enablebit_t *e = &(d->enablebits[port]);
606 if (e->reg && (pci_read_config_byte(dev, e->reg, &tmp) || (tmp & e->mask) != e->val))
607 continue; /* port not enabled */
608 if (IDE_PCI_DEVID_EQ(d->devid, DEVID_HPT366) && (port) && (class_rev < 0x03))
609 return;
610 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE || (dev->class & (port ? 4 : 1)) != 0) {
611 ctl = dev->resource[(2*port)+1].start;
612 base = dev->resource[2*port].start;
613 if (!(ctl & PCI_BASE_ADDRESS_IO_MASK) ||
614 !(base & PCI_BASE_ADDRESS_IO_MASK)) {
615 printk("%s: IO baseregs (BIOS) are reported as MEM, report to <andre@linux-ide.org>.\n", d->name);
616 #if 0
617 /* FIXME! This really should check that it really gets the IO/MEM part right! */
618 continue;
619 #endif
620 }
621 }
622 if ((ctl && !base) || (base && !ctl)) {
623 printk("%s: inconsistent baseregs (BIOS) for port %d, skipping\n", d->name, port);
624 continue;
625 }
626 if (!ctl)
627 ctl = port ? 0x374 : 0x3f4; /* use default value */
628 if (!base)
629 base = port ? 0x170 : 0x1f0; /* use default value */
630 if ((hwif = ide_match_hwif(base, d->bootable, d->name)) == NULL)
631 continue; /* no room in ide_hwifs[] */
632 if (hwif->io_ports[IDE_DATA_OFFSET] != base) {
633 ide_init_hwif_ports(&hwif->hw, base, (ctl | 2), NULL);
634 memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->io_ports));
635 hwif->noprobe = !hwif->io_ports[IDE_DATA_OFFSET];
636 }
637 hwif->chipset = ide_pci;
638 hwif->pci_dev = dev;
639 hwif->pci_devid = d->devid;
640 hwif->channel = port;
641 if (!hwif->irq)
642 hwif->irq = pciirq;
643 if (mate) {
644 hwif->mate = mate;
645 mate->mate = hwif;
646 if (IDE_PCI_DEVID_EQ(d->devid, DEVID_AEC6210)) {
647 hwif->serialized = 1;
648 mate->serialized = 1;
649 }
650 }
651 if (IDE_PCI_DEVID_EQ(d->devid, DEVID_UM8886A) ||
652 IDE_PCI_DEVID_EQ(d->devid, DEVID_UM8886BF) ||
653 IDE_PCI_DEVID_EQ(d->devid, DEVID_UM8673F)) {
654 hwif->irq = hwif->channel ? 15 : 14;
655 goto bypass_umc_dma;
656 }
657 if (hwif->udma_four) {
658 printk("%s: ATA-66/100 forced bit set (WARNING)!!\n", d->name);
659 } else {
660 hwif->udma_four = (d->ata66_check) ? d->ata66_check(hwif) : 0;
661 }
662 #ifdef CONFIG_BLK_DEV_IDEDMA
663 if (IDE_PCI_DEVID_EQ(d->devid, DEVID_SIS5513) ||
664 IDE_PCI_DEVID_EQ(d->devid, DEVID_AEC6260) ||
665 IDE_PCI_DEVID_EQ(d->devid, DEVID_PIIX4NX) ||
666 IDE_PCI_DEVID_EQ(d->devid, DEVID_HPT34X))
667 autodma = 0;
668 if (autodma)
669 hwif->autodma = 1;
670 if (IDE_PCI_DEVID_EQ(d->devid, DEVID_PDC20246) ||
671 IDE_PCI_DEVID_EQ(d->devid, DEVID_PDC20262) ||
672 IDE_PCI_DEVID_EQ(d->devid, DEVID_PDC20265) ||
673 IDE_PCI_DEVID_EQ(d->devid, DEVID_PDC20267) ||
674 IDE_PCI_DEVID_EQ(d->devid, DEVID_AEC6210) ||
675 IDE_PCI_DEVID_EQ(d->devid, DEVID_AEC6260) ||
676 IDE_PCI_DEVID_EQ(d->devid, DEVID_AEC6260R) ||
677 IDE_PCI_DEVID_EQ(d->devid, DEVID_HPT34X) ||
678 IDE_PCI_DEVID_EQ(d->devid, DEVID_HPT366) ||
679 IDE_PCI_DEVID_EQ(d->devid, DEVID_CS5530) ||
680 IDE_PCI_DEVID_EQ(d->devid, DEVID_CY82C693) ||
681 IDE_PCI_DEVID_EQ(d->devid, DEVID_CMD646) ||
682 IDE_PCI_DEVID_EQ(d->devid, DEVID_CMD648) ||
683 IDE_PCI_DEVID_EQ(d->devid, DEVID_CMD649) ||
684 IDE_PCI_DEVID_EQ(d->devid, DEVID_OSB4) ||
685 ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE && (dev->class & 0x80))) {
686 unsigned long dma_base = ide_get_or_set_dma_base(hwif, (!mate && d->extra) ? d->extra : 0, d->name);
687 if (dma_base && !(pcicmd & PCI_COMMAND_MASTER)) {
688 /*
689 * Set up BM-DMA capability (PnP BIOS should have done this)
690 */
691 hwif->autodma = 0; /* default DMA off if we had to configure it here */
692 (void) pci_write_config_word(dev, PCI_COMMAND, pcicmd | PCI_COMMAND_MASTER);
693 if (pci_read_config_word(dev, PCI_COMMAND, &pcicmd) || !(pcicmd & PCI_COMMAND_MASTER)) {
694 printk("%s: %s error updating PCICMD\n", hwif->name, d->name);
695 dma_base = 0;
696 }
697 }
698 if (dma_base) {
699 if (d->dma_init) {
700 d->dma_init(hwif, dma_base);
701 } else {
702 ide_setup_dma(hwif, dma_base, 8);
703 }
704 } else {
705 printk("%s: %s Bus-Master DMA disabled (BIOS)\n", hwif->name, d->name);
706 }
707 }
708 #endif /* CONFIG_BLK_DEV_IDEDMA */
709 bypass_umc_dma:
710 if (d->init_hwif) /* Call chipset-specific routine for each enabled hwif */
711 d->init_hwif(hwif);
712 mate = hwif;
713 at_least_one_hwif_enabled = 1;
714 }
715 if (!at_least_one_hwif_enabled)
716 printk("%s: neither IDE port enabled (BIOS)\n", d->name);
717 }
718
719 static void __init hpt366_device_order_fixup (struct pci_dev *dev, ide_pci_device_t *d)
720 {
721 struct pci_dev *dev2 = NULL, *findev;
722 ide_pci_device_t *d2;
723 unsigned char pin1 = 0, pin2 = 0;
724 unsigned int class_rev;
725 char *chipset_names[] = {"HPT366", "HPT366", "HPT368", "HPT370", "HPT370A"};
726
727 if (PCI_FUNC(dev->devfn) & 1)
728 return;
729
730 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
731 class_rev &= 0xff;
732
733 strcpy(d->name, chipset_names[class_rev]);
734
735 switch(class_rev) {
736 case 4:
737 case 3: printk("%s: IDE controller on PCI bus %02x dev %02x\n", d->name, dev->bus->number, dev->devfn);
738 ide_setup_pci_device(dev, d);
739 return;
740 default: break;
741 }
742
743 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1);
744 pci_for_each_dev(findev) {
745 if ((findev->vendor == dev->vendor) &&
746 (findev->device == dev->device) &&
747 ((findev->devfn - dev->devfn) == 1) &&
748 (PCI_FUNC(findev->devfn) & 1)) {
749 dev2 = findev;
750 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin2);
751 hpt363_shared_pin = (pin1 != pin2) ? 1 : 0;
752 hpt363_shared_irq = (dev->irq == dev2->irq) ? 1 : 0;
753 if (hpt363_shared_pin && hpt363_shared_irq) {
754 d->bootable = ON_BOARD;
755 printk("%s: onboard version of chipset, pin1=%d pin2=%d\n", d->name, pin1, pin2);
756 }
757 break;
758 }
759 }
760 printk("%s: IDE controller on PCI bus %02x dev %02x\n", d->name, dev->bus->number, dev->devfn);
761 ide_setup_pci_device(dev, d);
762 if (!dev2)
763 return;
764 d2 = d;
765 printk("%s: IDE controller on PCI bus %02x dev %02x\n", d2->name, dev2->bus->number, dev2->devfn);
766 ide_setup_pci_device(dev2, d2);
767 }
768
769 /*
770 * ide_scan_pcibus() gets invoked at boot time from ide.c.
771 * It finds all PCI IDE controllers and calls ide_setup_pci_device for them.
772 */
773 void __init ide_scan_pcidev (struct pci_dev *dev)
774 {
775 ide_pci_devid_t devid;
776 ide_pci_device_t *d;
777
778 devid.vid = dev->vendor;
779 devid.did = dev->device;
780 for (d = ide_pci_chipsets; d->devid.vid && !IDE_PCI_DEVID_EQ(d->devid, devid); ++d);
781 if (d->init_hwif == IDE_IGNORE)
782 printk("%s: ignored by ide_scan_pci_device() (uses own driver)\n", d->name);
783 else if (IDE_PCI_DEVID_EQ(d->devid, DEVID_OPTI621V) && !(PCI_FUNC(dev->devfn) & 1))
784 return;
785 else if (IDE_PCI_DEVID_EQ(d->devid, DEVID_CY82C693) && (!(PCI_FUNC(dev->devfn) & 1) || !((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)))
786 return; /* CY82C693 is more than only a IDE controller */
787 else if (IDE_PCI_DEVID_EQ(d->devid, DEVID_UM8886A) && !(PCI_FUNC(dev->devfn) & 1))
788 return; /* UM8886A/BF pair */
789 else if (IDE_PCI_DEVID_EQ(d->devid, DEVID_HPT366))
790 hpt366_device_order_fixup(dev, d);
791 else if (!IDE_PCI_DEVID_EQ(d->devid, IDE_PCI_DEVID_NULL) || (dev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
792 if (IDE_PCI_DEVID_EQ(d->devid, IDE_PCI_DEVID_NULL))
793 printk("%s: unknown IDE controller on PCI bus %02x device %02x, VID=%04x, DID=%04x\n",
794 d->name, dev->bus->number, dev->devfn, devid.vid, devid.did);
795 else
796 printk("%s: IDE controller on PCI bus %02x dev %02x\n", d->name, dev->bus->number, dev->devfn);
797 ide_setup_pci_device(dev, d);
798 }
799 }
800
801 void __init ide_scan_pcibus (int scan_direction)
802 {
803 struct pci_dev *dev;
804
805 if (!scan_direction) {
806 pci_for_each_dev(dev) {
807 ide_scan_pcidev(dev);
808 }
809 } else {
810 pci_for_each_dev_reverse(dev) {
811 ide_scan_pcidev(dev);
812 }
813 }
814 }
815
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