1 /*
2 * linux/drivers/ide/hpt366.c Version 0.18 June. 9, 2000
3 *
4 * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org>
5 * May be copied or modified under the terms of the GNU General Public License
6 *
7 * Thanks to HighPoint Technologies for their assistance, and hardware.
8 * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
9 * donation of an ABit BP6 mainboard, processor, and memory acellerated
10 * development and support.
11 *
12 * Note that final HPT370 support was done by force extraction of GPL.
13 *
14 */
15
16 #include <linux/config.h>
17 #include <linux/types.h>
18 #include <linux/kernel.h>
19 #include <linux/delay.h>
20 #include <linux/timer.h>
21 #include <linux/mm.h>
22 #include <linux/ioport.h>
23 #include <linux/blkdev.h>
24 #include <linux/hdreg.h>
25
26 #include <linux/interrupt.h>
27 #include <linux/pci.h>
28 #include <linux/init.h>
29 #include <linux/ide.h>
30
31 #include <asm/io.h>
32 #include <asm/irq.h>
33
34 #include "ide_modes.h"
35
36 #define DISPLAY_HPT366_TIMINGS
37
38 #if defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS)
39 #include <linux/stat.h>
40 #include <linux/proc_fs.h>
41 #endif /* defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS) */
42
43 extern char *ide_dmafunc_verbose(ide_dma_action_t dmafunc);
44
45 const char *quirk_drives[] = {
46 "QUANTUM FIREBALLlct08 08",
47 "QUANTUM FIREBALLP KA6.4",
48 "QUANTUM FIREBALLP LM20.4",
49 "QUANTUM FIREBALLP LM20.5",
50 NULL
51 };
52
53 const char *bad_ata100_5[] = {
54 NULL
55 };
56
57 const char *bad_ata66_4[] = {
58 "IBM-DTLA-307075",
59 "IBM-DTLA-307060",
60 "IBM-DTLA-307045",
61 "IBM-DTLA-307030",
62 "IBM-DTLA-307020",
63 "IBM-DTLA-307015",
64 "IBM-DTLA-305040",
65 "IBM-DTLA-305030",
66 "IBM-DTLA-305020",
67 "WDC AC310200R",
68 NULL
69 };
70
71 const char *bad_ata66_3[] = {
72 "WDC AC310200R",
73 NULL
74 };
75
76 const char *bad_ata33[] = {
77 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
78 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
79 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
80 "Maxtor 90510D4",
81 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
82 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
83 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
84 NULL
85 };
86
87 struct chipset_bus_clock_list_entry {
88 byte xfer_speed;
89 unsigned int chipset_settings_write;
90 unsigned int chipset_settings_read;
91 };
92
93 struct chipset_bus_clock_list_entry forty_base [] = {
94
95 { XFER_UDMA_4, 0x900fd943, 0x900fd943 },
96 { XFER_UDMA_3, 0x900ad943, 0x900ad943 },
97 { XFER_UDMA_2, 0x900bd943, 0x900bd943 },
98 { XFER_UDMA_1, 0x9008d943, 0x9008d943 },
99 { XFER_UDMA_0, 0x9008d943, 0x9008d943 },
100
101 { XFER_MW_DMA_2, 0xa008d943, 0xa008d943 },
102 { XFER_MW_DMA_1, 0xa010d955, 0xa010d955 },
103 { XFER_MW_DMA_0, 0xa010d9fc, 0xa010d9fc },
104
105 { XFER_PIO_4, 0xc008d963, 0xc008d963 },
106 { XFER_PIO_3, 0xc010d974, 0xc010d974 },
107 { XFER_PIO_2, 0xc010d997, 0xc010d997 },
108 { XFER_PIO_1, 0xc010d9c7, 0xc010d9c7 },
109 { XFER_PIO_0, 0xc018d9d9, 0xc018d9d9 },
110 { 0, 0x0120d9d9, 0x0120d9d9 }
111 };
112
113 struct chipset_bus_clock_list_entry thirty_three_base [] = {
114
115 { XFER_UDMA_4, 0x90c9a731, 0x90c9a731 },
116 { XFER_UDMA_3, 0x90cfa731, 0x90cfa731 },
117 { XFER_UDMA_2, 0x90caa731, 0x90caa731 },
118 { XFER_UDMA_1, 0x90cba731, 0x90cba731 },
119 { XFER_UDMA_0, 0x90c8a731, 0x90c8a731 },
120
121 { XFER_MW_DMA_2, 0xa0c8a731, 0xa0c8a731 },
122 { XFER_MW_DMA_1, 0xa0c8a732, 0xa0c8a732 }, /* 0xa0c8a733 */
123 { XFER_MW_DMA_0, 0xa0c8a797, 0xa0c8a797 },
124
125 { XFER_PIO_4, 0xc0c8a731, 0xc0c8a731 },
126 { XFER_PIO_3, 0xc0c8a742, 0xc0c8a742 },
127 { XFER_PIO_2, 0xc0d0a753, 0xc0d0a753 },
128 { XFER_PIO_1, 0xc0d0a7a3, 0xc0d0a7a3 }, /* 0xc0d0a793 */
129 { XFER_PIO_0, 0xc0d0a7aa, 0xc0d0a7aa }, /* 0xc0d0a7a7 */
130 { 0, 0x0120a7a7, 0x0120a7a7 }
131 };
132
133 struct chipset_bus_clock_list_entry twenty_five_base [] = {
134
135 { XFER_UDMA_4, 0x90c98521, 0x90c98521 },
136 { XFER_UDMA_3, 0x90cf8521, 0x90cf8521 },
137 { XFER_UDMA_2, 0x90cf8521, 0x90cf8521 },
138 { XFER_UDMA_1, 0x90cb8521, 0x90cb8521 },
139 { XFER_UDMA_0, 0x90cb8521, 0x90cb8521 },
140
141 { XFER_MW_DMA_2, 0xa0ca8521, 0xa0ca8521 },
142 { XFER_MW_DMA_1, 0xa0ca8532, 0xa0ca8532 },
143 { XFER_MW_DMA_0, 0xa0ca8575, 0xa0ca8575 },
144
145 { XFER_PIO_4, 0xc0ca8521, 0xc0ca8521 },
146 { XFER_PIO_3, 0xc0ca8532, 0xc0ca8532 },
147 { XFER_PIO_2, 0xc0ca8542, 0xc0ca8542 },
148 { XFER_PIO_1, 0xc0d08572, 0xc0d08572 },
149 { XFER_PIO_0, 0xc0d08585, 0xc0d08585 },
150 { 0, 0x01208585, 0x01208585 }
151 };
152
153 struct chipset_bus_clock_list_entry thirty_three_base_hpt370[] = {
154 { XFER_UDMA_5, 0x1A85F442, 0x16454e31 },
155 { XFER_UDMA_4, 0x16454e31, 0x16454e31 },
156 { XFER_UDMA_3, 0x166d4e31, 0x166d4e31 },
157 { XFER_UDMA_2, 0x16494e31, 0x16494e31 },
158 { XFER_UDMA_1, 0x164d4e31, 0x164d4e31 },
159 { XFER_UDMA_0, 0x16514e31, 0x16514e31 },
160
161 { XFER_MW_DMA_2, 0x26514e21, 0x26514e21 },
162 { XFER_MW_DMA_1, 0x26514e33, 0x26514e33 },
163 { XFER_MW_DMA_0, 0x26514e97, 0x26514e97 },
164
165 { XFER_PIO_4, 0x06514e21, 0x06514e21 },
166 { XFER_PIO_3, 0x06514e22, 0x06514e22 },
167 { XFER_PIO_2, 0x06514e33, 0x06514e33 },
168 { XFER_PIO_1, 0x06914e43, 0x06914e43 },
169 { XFER_PIO_0, 0x06914e57, 0x06914e57 },
170 { 0, 0x06514e57, 0x06514e57 }
171 };
172
173 #define HPT366_DEBUG_DRIVE_INFO 0
174 #define HPT370_ALLOW_ATA100_5 1
175 #define HPT366_ALLOW_ATA66_4 1
176 #define HPT366_ALLOW_ATA66_3 1
177
178 #if defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS)
179 static int hpt366_get_info(char *, char **, off_t, int);
180 extern int (*hpt366_display_info)(char *, char **, off_t, int); /* ide-proc.c */
181 extern char *ide_media_verbose(ide_drive_t *);
182 static struct pci_dev *bmide_dev;
183 static struct pci_dev *bmide2_dev;
184
185 static int hpt366_get_info (char *buffer, char **addr, off_t offset, int count)
186 {
187 char *p = buffer;
188 u32 bibma = bmide_dev->resource[4].start;
189 u32 bibma2 = bmide2_dev->resource[4].start;
190 char *chipset_names[] = {"HPT366", "HPT366", "HPT368", "HPT370", "HPT370A"};
191 u8 c0 = 0, c1 = 0;
192 u32 class_rev;
193
194 pci_read_config_dword(bmide_dev, PCI_CLASS_REVISION, &class_rev);
195 class_rev &= 0xff;
196
197 /*
198 * at that point bibma+0x2 et bibma+0xa are byte registers
199 * to investigate:
200 */
201 c0 = inb_p((unsigned short)bibma + 0x02);
202 if (bmide2_dev)
203 c1 = inb_p((unsigned short)bibma2 + 0x02);
204
205 p += sprintf(p, "\n %s Chipset.\n", chipset_names[class_rev]);
206 p += sprintf(p, "--------------- Primary Channel ---------------- Secondary Channel -------------\n");
207 p += sprintf(p, " %sabled %sabled\n",
208 (c0&0x80) ? "dis" : " en",
209 (c1&0x80) ? "dis" : " en");
210 p += sprintf(p, "--------------- drive0 --------- drive1 -------- drive0 ---------- drive1 ------\n");
211 p += sprintf(p, "DMA enabled: %s %s %s %s\n",
212 (c0&0x20) ? "yes" : "no ", (c0&0x40) ? "yes" : "no ",
213 (c1&0x20) ? "yes" : "no ", (c1&0x40) ? "yes" : "no " );
214
215 p += sprintf(p, "UDMA\n");
216 p += sprintf(p, "DMA\n");
217 p += sprintf(p, "PIO\n");
218
219 return p-buffer;/* => must be less than 4k! */
220 }
221 #endif /* defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS) */
222
223 byte hpt366_proc = 0;
224
225 extern char *ide_xfer_verbose (byte xfer_rate);
226 byte hpt363_shared_irq = 0;
227 byte hpt363_shared_pin = 0;
228
229 static unsigned int pci_rev_check_hpt3xx (struct pci_dev *dev)
230 {
231 unsigned int class_rev;
232 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
233 class_rev &= 0xff;
234 return ((int) (class_rev > 0x02) ? 1 : 0);
235 }
236
237 static unsigned int pci_rev2_check_hpt3xx (struct pci_dev *dev)
238 {
239 unsigned int class_rev;
240 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
241 class_rev &= 0xff;
242 return ((int) (class_rev > 0x01) ? 1 : 0);
243 }
244
245 static int check_in_drive_lists (ide_drive_t *drive, const char **list)
246 {
247 struct hd_driveid *id = drive->id;
248
249 if (quirk_drives == list) {
250 while (*list) {
251 if (strstr(id->model, *list++)) {
252 return 1;
253 }
254 }
255 } else {
256 while (*list) {
257 if (!strcmp(*list++,id->model)) {
258 return 1;
259 }
260 }
261 }
262 return 0;
263 }
264
265 static unsigned int pci_bus_clock_list (byte speed, int direction, struct chipset_bus_clock_list_entry * chipset_table)
266 {
267 for ( ; chipset_table->xfer_speed ; chipset_table++)
268 if (chipset_table->xfer_speed == speed) {
269 return (direction) ? chipset_table->chipset_settings_write : chipset_table->chipset_settings_read;
270 }
271 return (direction) ? chipset_table->chipset_settings_write : chipset_table->chipset_settings_read;
272 }
273
274 static void hpt366_tune_chipset (ide_drive_t *drive, byte speed, int direction)
275 {
276 byte regtime = (drive->select.b.unit & 0x01) ? 0x44 : 0x40;
277 byte regfast = (HWIF(drive)->channel) ? 0x55 : 0x51;
278 /*
279 * since the channel is always 0 it does not matter.
280 */
281
282 unsigned int reg1 = 0;
283 unsigned int reg2 = 0;
284 byte drive_fast = 0;
285
286 /*
287 * Disable the "fast interrupt" prediction.
288 */
289 pci_read_config_byte(HWIF(drive)->pci_dev, regfast, &drive_fast);
290 if (drive_fast & 0x02)
291 pci_write_config_byte(HWIF(drive)->pci_dev, regfast, drive_fast & ~0x20);
292
293 pci_read_config_dword(HWIF(drive)->pci_dev, regtime, ®1);
294 /* detect bus speed by looking at control reg timing: */
295 switch((reg1 >> 8) & 7) {
296 case 5:
297 reg2 = pci_bus_clock_list(speed, direction, forty_base);
298 break;
299 case 9:
300 reg2 = pci_bus_clock_list(speed, direction, twenty_five_base);
301 break;
302 default:
303 case 7:
304 reg2 = pci_bus_clock_list(speed, direction, thirty_three_base);
305 break;
306 }
307 /*
308 * Disable on-chip PIO FIFO/buffer (to avoid problems handling I/O errors later)
309 */
310 if (speed >= XFER_MW_DMA_0) {
311 reg2 = (reg2 & ~0xc0000000) | (reg1 & 0xc0000000);
312 } else {
313 reg2 = (reg2 & ~0x30070000) | (reg1 & 0x30070000);
314 }
315 reg2 &= ~0x80000000;
316
317 pci_write_config_dword(HWIF(drive)->pci_dev, regtime, reg2);
318 }
319
320 static void hpt370_tune_chipset (ide_drive_t *drive, byte speed, int direction)
321 {
322 byte regfast = (HWIF(drive)->channel) ? 0x55 : 0x51;
323 byte reg5bh = (speed != XFER_UDMA_5) ? 0x22 : (direction) ? 0x20 : 0x22;
324 unsigned int list_conf = pci_bus_clock_list(speed, direction, thirty_three_base_hpt370);
325 unsigned int drive_conf = 0;
326 unsigned int conf_mask = (speed >= XFER_MW_DMA_0) ? 0xc0000000 : 0x30070000;
327 byte drive_pci = 0;
328 byte drive_fast = 0;
329
330 switch (drive->dn) {
331 case 0: drive_pci = 0x40; break;
332 case 1: drive_pci = 0x44; break;
333 case 2: drive_pci = 0x48; break;
334 case 3: drive_pci = 0x4c; break;
335 default: return;
336 }
337 /*
338 * Disable the "fast interrupt" prediction.
339 */
340 pci_read_config_byte(HWIF(drive)->pci_dev, regfast, &drive_fast);
341 if (drive_fast & 0x80)
342 pci_write_config_byte(HWIF(drive)->pci_dev, regfast, drive_fast & ~0x80);
343
344 pci_read_config_dword(HWIF(drive)->pci_dev, drive_pci, &drive_conf);
345 pci_write_config_byte(HWIF(drive)->pci_dev, 0x5b, reg5bh);
346
347 list_conf = (list_conf & ~conf_mask) | (drive_conf & conf_mask);
348 /*
349 * Disable on-chip PIO FIFO/buffer (to avoid problems handling I/O errors later)
350 */
351 list_conf &= ~0x80000000;
352
353 pci_write_config_dword(HWIF(drive)->pci_dev, drive_pci, list_conf);
354 }
355
356 static int hpt3xx_tune_chipset (ide_drive_t *drive, byte speed)
357 {
358 if ((drive->media != ide_disk) && (speed < XFER_SW_DMA_0))
359 return -1;
360
361 if (!drive->init_speed)
362 drive->init_speed = speed;
363
364 if (pci_rev_check_hpt3xx(HWIF(drive)->pci_dev)) {
365 hpt370_tune_chipset(drive, speed, 0);
366 } else {
367 hpt366_tune_chipset(drive, speed, 0);
368 }
369 drive->current_speed = speed;
370 return ((int) ide_config_drive_speed(drive, speed));
371 }
372
373 static void config_chipset_for_pio (ide_drive_t *drive)
374 {
375 unsigned short eide_pio_timing[6] = {960, 480, 240, 180, 120, 90};
376 unsigned short xfer_pio = drive->id->eide_pio_modes;
377 byte timing, speed, pio;
378
379 pio = ide_get_best_pio_mode(drive, 255, 5, NULL);
380
381 if (xfer_pio> 4)
382 xfer_pio = 0;
383
384 if (drive->id->eide_pio_iordy > 0) {
385 for (xfer_pio = 5;
386 xfer_pio>0 &&
387 drive->id->eide_pio_iordy>eide_pio_timing[xfer_pio];
388 xfer_pio--);
389 } else {
390 xfer_pio = (drive->id->eide_pio_modes & 4) ? 0x05 :
391 (drive->id->eide_pio_modes & 2) ? 0x04 :
392 (drive->id->eide_pio_modes & 1) ? 0x03 :
393 (drive->id->tPIO & 2) ? 0x02 :
394 (drive->id->tPIO & 1) ? 0x01 : xfer_pio;
395 }
396
397 timing = (xfer_pio >= pio) ? xfer_pio : pio;
398
399 switch(timing) {
400 case 4: speed = XFER_PIO_4;break;
401 case 3: speed = XFER_PIO_3;break;
402 case 2: speed = XFER_PIO_2;break;
403 case 1: speed = XFER_PIO_1;break;
404 default:
405 speed = (!drive->id->tPIO) ? XFER_PIO_0 : XFER_PIO_SLOW;
406 break;
407 }
408 (void) hpt3xx_tune_chipset(drive, speed);
409 }
410
411 static void hpt3xx_tune_drive (ide_drive_t *drive, byte pio)
412 {
413 byte speed;
414 switch(pio) {
415 case 4: speed = XFER_PIO_4;break;
416 case 3: speed = XFER_PIO_3;break;
417 case 2: speed = XFER_PIO_2;break;
418 case 1: speed = XFER_PIO_1;break;
419 default: speed = XFER_PIO_0;break;
420 }
421 (void) hpt3xx_tune_chipset(drive, speed);
422 }
423
424 #ifdef CONFIG_BLK_DEV_IDEDMA
425 /*
426 * This allows the configuration of ide_pci chipset registers
427 * for cards that learn about the drive's UDMA, DMA, PIO capabilities
428 * after the drive is reported by the OS. Initally for designed for
429 * HPT366 UDMA chipset by HighPoint|Triones Technologies, Inc.
430 *
431 * check_in_drive_lists(drive, bad_ata66_4)
432 * check_in_drive_lists(drive, bad_ata66_3)
433 * check_in_drive_lists(drive, bad_ata33)
434 *
435 */
436 static int config_chipset_for_dma (ide_drive_t *drive)
437 {
438 struct hd_driveid *id = drive->id;
439 byte speed = 0x00;
440 byte ultra66 = eighty_ninty_three(drive);
441 int rval;
442
443 if ((drive->media != ide_disk) && (speed < XFER_SW_DMA_0))
444 return ((int) ide_dma_off_quietly);
445
446 if ((id->dma_ultra & 0x0020) &&
447 (!check_in_drive_lists(drive, bad_ata100_5)) &&
448 (HPT370_ALLOW_ATA100_5) &&
449 (pci_rev_check_hpt3xx(HWIF(drive)->pci_dev)) &&
450 (ultra66)) {
451 speed = XFER_UDMA_5;
452 } else if ((id->dma_ultra & 0x0010) &&
453 (!check_in_drive_lists(drive, bad_ata66_4)) &&
454 (HPT366_ALLOW_ATA66_4) &&
455 (ultra66)) {
456 speed = XFER_UDMA_4;
457 } else if ((id->dma_ultra & 0x0008) &&
458 (!check_in_drive_lists(drive, bad_ata66_3)) &&
459 (HPT366_ALLOW_ATA66_3) &&
460 (ultra66)) {
461 speed = XFER_UDMA_3;
462 } else if (id->dma_ultra && (!check_in_drive_lists(drive, bad_ata33))) {
463 if (id->dma_ultra & 0x0004) {
464 speed = XFER_UDMA_2;
465 } else if (id->dma_ultra & 0x0002) {
466 speed = XFER_UDMA_1;
467 } else if (id->dma_ultra & 0x0001) {
468 speed = XFER_UDMA_0;
469 }
470 } else if (id->dma_mword & 0x0004) {
471 speed = XFER_MW_DMA_2;
472 } else if (id->dma_mword & 0x0002) {
473 speed = XFER_MW_DMA_1;
474 } else if (id->dma_mword & 0x0001) {
475 speed = XFER_MW_DMA_0;
476 } else {
477 return ((int) ide_dma_off_quietly);
478 }
479
480 (void) hpt3xx_tune_chipset(drive, speed);
481
482 rval = (int)( ((id->dma_ultra >> 11) & 7) ? ide_dma_on :
483 ((id->dma_ultra >> 8) & 7) ? ide_dma_on :
484 ((id->dma_mword >> 8) & 7) ? ide_dma_on :
485 ide_dma_off_quietly);
486 return rval;
487 }
488
489 int hpt3xx_quirkproc (ide_drive_t *drive)
490 {
491 return ((int) check_in_drive_lists(drive, quirk_drives));
492 }
493
494 void hpt3xx_intrproc (ide_drive_t *drive)
495 {
496 if (drive->quirk_list) {
497 /* drives in the quirk_list may not like intr setups/cleanups */
498 } else {
499 OUT_BYTE((drive)->ctl|2, HWIF(drive)->io_ports[IDE_CONTROL_OFFSET]);
500 }
501 }
502
503 void hpt3xx_maskproc (ide_drive_t *drive, int mask)
504 {
505 if (drive->quirk_list) {
506 if (pci_rev_check_hpt3xx(HWIF(drive)->pci_dev)) {
507 byte reg5a = 0;
508 pci_read_config_byte(HWIF(drive)->pci_dev, 0x5a, ®5a);
509 if (((reg5a & 0x10) >> 4) != mask)
510 pci_write_config_byte(HWIF(drive)->pci_dev, 0x5a, mask ? (reg5a | 0x10) : (reg5a & ~0x10));
511 } else {
512 if (mask) {
513 disable_irq(HWIF(drive)->irq);
514 } else {
515 enable_irq(HWIF(drive)->irq);
516 }
517 }
518 } else {
519 if (IDE_CONTROL_REG)
520 OUT_BYTE(mask ? (drive->ctl | 2) : (drive->ctl & ~2), IDE_CONTROL_REG);
521 }
522 }
523
524 void hpt370_rw_proc (ide_drive_t *drive, ide_dma_action_t func)
525 {
526 if ((func != ide_dma_write) || (func != ide_dma_read))
527 return;
528 hpt370_tune_chipset(drive, drive->current_speed, (func == ide_dma_write));
529 }
530
531 static int config_drive_xfer_rate (ide_drive_t *drive)
532 {
533 struct hd_driveid *id = drive->id;
534 ide_dma_action_t dma_func = ide_dma_on;
535
536 if (id && (id->capability & 1) && HWIF(drive)->autodma) {
537 /* Consult the list of known "bad" drives */
538 if (ide_dmaproc(ide_dma_bad_drive, drive)) {
539 dma_func = ide_dma_off;
540 goto fast_ata_pio;
541 }
542 dma_func = ide_dma_off_quietly;
543 if (id->field_valid & 4) {
544 if (id->dma_ultra & 0x002F) {
545 /* Force if Capable UltraDMA */
546 dma_func = config_chipset_for_dma(drive);
547 if ((id->field_valid & 2) &&
548 (dma_func != ide_dma_on))
549 goto try_dma_modes;
550 }
551 } else if (id->field_valid & 2) {
552 try_dma_modes:
553 if (id->dma_mword & 0x0007) {
554 /* Force if Capable regular DMA modes */
555 dma_func = config_chipset_for_dma(drive);
556 if (dma_func != ide_dma_on)
557 goto no_dma_set;
558 }
559 } else if (ide_dmaproc(ide_dma_good_drive, drive)) {
560 if (id->eide_dma_time > 150) {
561 goto no_dma_set;
562 }
563 /* Consult the list of known "good" drives */
564 dma_func = config_chipset_for_dma(drive);
565 if (dma_func != ide_dma_on)
566 goto no_dma_set;
567 } else {
568 goto fast_ata_pio;
569 }
570 } else if ((id->capability & 8) || (id->field_valid & 2)) {
571 fast_ata_pio:
572 dma_func = ide_dma_off_quietly;
573 no_dma_set:
574
575 config_chipset_for_pio(drive);
576 }
577 return HWIF(drive)->dmaproc(dma_func, drive);
578 }
579
580 /*
581 * hpt366_dmaproc() initiates/aborts (U)DMA read/write operations on a drive.
582 *
583 * This is specific to the HPT366 UDMA bios chipset
584 * by HighPoint|Triones Technologies, Inc.
585 */
586 int hpt366_dmaproc (ide_dma_action_t func, ide_drive_t *drive)
587 {
588 byte reg50h = 0, reg52h = 0, reg5ah = 0, dma_stat = 0;
589 unsigned long dma_base = HWIF(drive)->dma_base;
590
591 switch (func) {
592 case ide_dma_check:
593 return config_drive_xfer_rate(drive);
594 case ide_dma_test_irq: /* returns 1 if dma irq issued, 0 otherwise */
595 dma_stat = inb(dma_base+2);
596 return (dma_stat & 4) == 4; /* return 1 if INTR asserted */
597 case ide_dma_lostirq:
598 pci_read_config_byte(HWIF(drive)->pci_dev, 0x50, ®50h);
599 pci_read_config_byte(HWIF(drive)->pci_dev, 0x52, ®52h);
600 pci_read_config_byte(HWIF(drive)->pci_dev, 0x5a, ®5ah);
601 printk("%s: (%s) reg50h=0x%02x, reg52h=0x%02x, reg5ah=0x%02x\n",
602 drive->name,
603 ide_dmafunc_verbose(func),
604 reg50h, reg52h, reg5ah);
605 if (reg5ah & 0x10)
606 pci_write_config_byte(HWIF(drive)->pci_dev, 0x5a, reg5ah & ~0x10);
607 break;
608 case ide_dma_timeout:
609 default:
610 break;
611 }
612 return ide_dmaproc(func, drive); /* use standard DMA stuff */
613 }
614
615 int hpt370_dmaproc (ide_dma_action_t func, ide_drive_t *drive)
616 {
617 switch (func) {
618 case ide_dma_check:
619 return config_drive_xfer_rate(drive);
620 default:
621 break;
622 }
623 return ide_dmaproc(func, drive); /* use standard DMA stuff */
624 }
625 #endif /* CONFIG_BLK_DEV_IDEDMA */
626
627 unsigned int __init pci_init_hpt366 (struct pci_dev *dev, const char *name)
628 {
629 byte test = 0;
630
631 if (dev->resource[PCI_ROM_RESOURCE].start)
632 pci_write_config_byte(dev, PCI_ROM_ADDRESS, dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
633
634 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &test);
635
636 #if 0
637 if (test != 0x08)
638 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x08);
639 #else
640 if (test != (L1_CACHE_BYTES / 4))
641 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
642 #endif
643
644 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &test);
645 if (test != 0x78)
646 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
647
648 pci_read_config_byte(dev, PCI_MIN_GNT, &test);
649 if (test != 0x08)
650 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
651
652 pci_read_config_byte(dev, PCI_MAX_LAT, &test);
653 if (test != 0x08)
654 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
655
656 #if defined(DISPLAY_HPT366_TIMINGS) && defined(CONFIG_PROC_FS)
657 if (!hpt366_proc) {
658 hpt366_proc = 1;
659 bmide_dev = dev;
660 if (pci_rev_check_hpt3xx(dev))
661 bmide2_dev = dev;
662 hpt366_display_info = &hpt366_get_info;
663 }
664 if ((hpt366_proc) && ((dev->devfn - bmide_dev->devfn) == 1)) {
665 bmide2_dev = dev;
666 }
667 #endif /* DISPLAY_HPT366_TIMINGS && CONFIG_PROC_FS */
668
669 return dev->irq;
670 }
671
672 unsigned int __init ata66_hpt366 (ide_hwif_t *hwif)
673 {
674 byte ata66 = 0;
675
676 pci_read_config_byte(hwif->pci_dev, 0x5a, &ata66);
677 #ifdef DEBUG
678 printk("HPT366: reg5ah=0x%02x ATA-%s Cable Port%d\n",
679 ata66, (ata66 & 0x02) ? "33" : "66",
680 PCI_FUNC(hwif->pci_dev->devfn));
681 #endif /* DEBUG */
682 return ((ata66 & 0x02) ? 0 : 1);
683 }
684
685 void __init ide_init_hpt366 (ide_hwif_t *hwif)
686 {
687 hwif->tuneproc = &hpt3xx_tune_drive;
688 hwif->speedproc = &hpt3xx_tune_chipset;
689 hwif->quirkproc = &hpt3xx_quirkproc;
690 hwif->intrproc = &hpt3xx_intrproc;
691 hwif->maskproc = &hpt3xx_maskproc;
692
693 if (pci_rev2_check_hpt3xx(hwif->pci_dev)) {
694 /* do nothing now but will split device types */
695 }
696
697 #ifdef CONFIG_BLK_DEV_IDEDMA
698 if (hwif->dma_base) {
699 if (pci_rev_check_hpt3xx(hwif->pci_dev)) {
700 byte reg5ah = 0;
701 pci_read_config_byte(hwif->pci_dev, 0x5a, ®5ah);
702 if (reg5ah & 0x10) /* interrupt force enable */
703 pci_write_config_byte(hwif->pci_dev, 0x5a, reg5ah & ~0x10);
704 hwif->dmaproc = &hpt370_dmaproc;
705 hwif->rwproc = &hpt370_rw_proc;
706 } else {
707 hwif->dmaproc = &hpt366_dmaproc;
708 }
709 hwif->autodma = 1;
710 } else {
711 hwif->autodma = 0;
712 hwif->drives[0].autotune = 1;
713 hwif->drives[1].autotune = 1;
714 }
715 #else /* !CONFIG_BLK_DEV_IDEDMA */
716 hwif->drives[0].autotune = 1;
717 hwif->drives[1].autotune = 1;
718 hwif->autodma = 0;
719 #endif /* CONFIG_BLK_DEV_IDEDMA */
720 }
721
722 void __init ide_dmacapable_hpt366 (ide_hwif_t *hwif, unsigned long dmabase)
723 {
724 byte masterdma = 0, slavedma = 0;
725 byte dma_new = 0, dma_old = inb(dmabase+2);
726 byte primary = hwif->channel ? 0x4b : 0x43;
727 byte secondary = hwif->channel ? 0x4f : 0x47;
728 unsigned long flags;
729
730 __save_flags(flags); /* local CPU only */
731 __cli(); /* local CPU only */
732
733 dma_new = dma_old;
734 pci_read_config_byte(hwif->pci_dev, primary, &masterdma);
735 pci_read_config_byte(hwif->pci_dev, secondary, &slavedma);
736
737 if (masterdma & 0x30) dma_new |= 0x20;
738 if (slavedma & 0x30) dma_new |= 0x40;
739 if (dma_new != dma_old) outb(dma_new, dmabase+2);
740
741 __restore_flags(flags); /* local CPU only */
742
743 ide_setup_dma(hwif, dmabase, 8);
744 }
745
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