1 /*
2 * Disk Array driver for Compaq SMART2 Controllers
3 * Copyright 1998 Compaq Computer Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
13 * NON INFRINGEMENT. See the GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 *
19 * Questions/Comments/Bugfixes to arrays@compaq.com
20 *
21 * If you want to make changes, improve or add functionality to this
22 * driver, you'll probably need the Compaq Array Controller Interface
23 * Specificiation (Document number ECG086/1198)
24 */
25 #ifndef ARRAYCMD_H
26 #define ARRAYCMD_H
27
28 #include <asm/types.h>
29 #if 0
30 #include <linux/blkdev.h>
31 #endif
32
33 /* for the Smart Array 42XX cards */
34 #define S42XX_REQUEST_PORT_OFFSET 0x40
35 #define S42XX_REPLY_INTR_MASK_OFFSET 0x34
36 #define S42XX_REPLY_PORT_OFFSET 0x44
37 #define S42XX_INTR_STATUS 0x30
38
39 #define S42XX_INTR_OFF 0x08
40 #define S42XX_INTR_PENDING 0x08
41
42 #define COMMAND_FIFO 0x04
43 #define COMMAND_COMPLETE_FIFO 0x08
44 #define INTR_MASK 0x0C
45 #define INTR_STATUS 0x10
46 #define INTR_PENDING 0x14
47
48 #define FIFO_NOT_EMPTY 0x01
49 #define FIFO_NOT_FULL 0x02
50
51 #define BIG_PROBLEM 0x40
52 #define LOG_NOT_CONF 2
53
54 #pragma pack(1)
55 typedef struct {
56 __u32 size;
57 __u32 addr;
58 } sg_t;
59
60 #define RCODE_NONFATAL 0x02
61 #define RCODE_FATAL 0x04
62 #define RCODE_INVREQ 0x10
63 typedef struct {
64 __u16 next;
65 __u8 cmd;
66 __u8 rcode;
67 __u32 blk;
68 __u16 blk_cnt;
69 __u8 sg_cnt;
70 __u8 reserved;
71 } rhdr_t;
72
73 #define SG_MAX 32
74 typedef struct {
75 rhdr_t hdr;
76 sg_t sg[SG_MAX];
77 __u32 bp;
78 } rblk_t;
79
80 typedef struct {
81 __u8 unit;
82 __u8 prio;
83 __u16 size;
84 } chdr_t;
85
86 #define CMD_RWREQ 0x00
87 #define CMD_IOCTL_PEND 0x01
88 #define CMD_IOCTL_DONE 0x02
89
90 typedef struct cmdlist {
91 chdr_t hdr;
92 rblk_t req;
93 __u32 size;
94 int retry_cnt;
95 __u32 busaddr;
96 int ctlr;
97 struct cmdlist *prev;
98 struct cmdlist *next;
99 struct buffer_head *bh;
100 int type;
101 } cmdlist_t;
102
103 #define ID_CTLR 0x11
104 typedef struct {
105 __u8 nr_drvs;
106 __u32 cfg_sig;
107 __u8 firm_rev[4];
108 __u8 rom_rev[4];
109 __u8 hw_rev;
110 __u32 bb_rev;
111 __u32 drv_present_map;
112 __u32 ext_drv_map;
113 __u32 board_id;
114 __u8 cfg_error;
115 __u32 non_disk_bits;
116 __u8 bad_ram_addr;
117 __u8 cpu_rev;
118 __u8 pdpi_rev;
119 __u8 epic_rev;
120 __u8 wcxc_rev;
121 __u8 marketing_rev;
122 __u8 ctlr_flags;
123 __u8 host_flags;
124 __u8 expand_dis;
125 __u8 scsi_chips;
126 __u32 max_req_blocks;
127 __u32 ctlr_clock;
128 __u8 drvs_per_bus;
129 __u16 big_drv_present_map[8];
130 __u16 big_ext_drv_map[8];
131 __u16 big_non_disk_map[8];
132 __u16 task_flags;
133 __u8 icl_bus;
134 __u8 red_modes;
135 __u8 cur_red_mode;
136 __u8 red_ctlr_stat;
137 __u8 red_fail_reason;
138 __u8 reserved[403];
139 } id_ctlr_t;
140
141 typedef struct {
142 __u16 cyl;
143 __u8 heads;
144 __u8 xsig;
145 __u8 psectors;
146 __u16 wpre;
147 __u8 maxecc;
148 __u8 drv_ctrl;
149 __u16 pcyls;
150 __u8 pheads;
151 __u16 landz;
152 __u8 sect_per_track;
153 __u8 cksum;
154 } drv_param_t;
155
156 #define ID_LOG_DRV 0x10
157 typedef struct {
158 __u16 blk_size;
159 __u32 nr_blks;
160 drv_param_t drv;
161 __u8 fault_tol;
162 __u8 reserved;
163 __u8 bios_disable;
164 } id_log_drv_t;
165
166 #define ID_LOG_DRV_EXT 0x18
167 typedef struct {
168 __u32 log_drv_id;
169 __u8 log_drv_label[64];
170 __u8 reserved[418];
171 } id_log_drv_ext_t;
172
173 #define SENSE_LOG_DRV_STAT 0x12
174 typedef struct {
175 __u8 status;
176 __u32 fail_map;
177 __u16 read_err[32];
178 __u16 write_err[32];
179 __u8 drv_err_data[256];
180 __u8 drq_timeout[32];
181 __u32 blks_to_recover;
182 __u8 drv_recovering;
183 __u16 remap_cnt[32];
184 __u32 replace_drv_map;
185 __u32 act_spare_map;
186 __u8 spare_stat;
187 __u8 spare_repl_map[32];
188 __u32 repl_ok_map;
189 __u8 media_exch;
190 __u8 cache_fail;
191 __u8 expn_fail;
192 __u8 unit_flags;
193 __u16 big_fail_map[8];
194 __u16 big_remap_map[128];
195 __u16 big_repl_map[8];
196 __u16 big_act_spare_map[8];
197 __u8 big_spar_repl_map[128];
198 __u16 big_repl_ok_map[8];
199 __u8 big_drv_rebuild;
200 __u8 reserved[36];
201 } sense_log_drv_stat_t;
202
203 #define START_RECOVER 0x13
204
205 #define ID_PHYS_DRV 0x15
206 typedef struct {
207 __u8 scsi_bus;
208 __u8 scsi_id;
209 __u16 blk_size;
210 __u32 nr_blks;
211 __u32 rsvd_blks;
212 __u8 drv_model[40];
213 __u8 drv_sn[40];
214 __u8 drv_fw[8];
215 __u8 scsi_iq_bits;
216 __u8 compaq_drv_stmp;
217 __u8 last_fail;
218 __u8 phys_drv_flags;
219 __u8 phys_drv_flags1;
220 __u8 scsi_lun;
221 __u8 phys_drv_flags2;
222 __u8 reserved;
223 __u32 spi_speed_rules;
224 __u8 phys_connector[2];
225 __u8 phys_box_on_bus;
226 __u8 phys_bay_in_box;
227 } id_phys_drv_t;
228
229 #define BLINK_DRV_LEDS 0x16
230 typedef struct {
231 __u32 blink_duration;
232 __u32 reserved;
233 __u8 blink[256];
234 __u8 reserved1[248];
235 } blink_drv_leds_t;
236
237 #define SENSE_BLINK_LEDS 0x17
238 typedef struct {
239 __u32 blink_duration;
240 __u32 btime_elap;
241 __u8 blink[256];
242 __u8 reserved1[248];
243 } sense_blink_leds_t;
244
245 #define IDA_READ 0x20
246 #define IDA_WRITE 0x30
247 #define IDA_WRITE_MEDIA 0x31
248 #define RESET_TO_DIAG 0x40
249 #define DIAG_PASS_THRU 0x41
250
251 #define SENSE_CONFIG 0x50
252 #define SET_CONFIG 0x51
253 typedef struct {
254 __u32 cfg_sig;
255 __u16 compat_port;
256 __u8 data_dist_mode;
257 __u8 surf_an_ctrl;
258 __u16 ctlr_phys_drv;
259 __u16 log_unit_phys_drv;
260 __u16 fault_tol_mode;
261 __u8 phys_drv_param[16];
262 drv_param_t drv;
263 __u32 drv_asgn_map;
264 __u16 dist_factor;
265 __u32 spare_asgn_map;
266 __u8 reserved[6];
267 __u16 os;
268 __u8 ctlr_order;
269 __u8 extra_info;
270 __u32 data_offs;
271 __u8 parity_backedout_write_drvs;
272 __u8 parity_dist_mode;
273 __u8 parity_shift_fact;
274 __u8 bios_disable_flag;
275 __u32 blks_on_vol;
276 __u32 blks_per_drv;
277 __u8 scratch[16];
278 __u16 big_drv_map[8];
279 __u16 big_spare_map[8];
280 __u8 ss_source_vol;
281 __u8 mix_drv_cap_range;
282 struct {
283 __u16 big_drv_map[8];
284 __u32 blks_per_drv;
285 __u16 fault_tol_mode;
286 __u16 dist_factor;
287 } MDC_range[4];
288 __u8 reserved1[248];
289 } config_t;
290
291 #define BYPASS_VOL_STATE 0x52
292 #define SS_CREATE_VOL 0x53
293 #define CHANGE_CONFIG 0x54
294 #define SENSE_ORIG_CONF 0x55
295 #define REORDER_LOG_DRV 0x56
296 typedef struct {
297 __u8 old_units[32];
298 } reorder_log_drv_t;
299
300 #define LABEL_LOG_DRV 0x57
301 typedef struct {
302 __u8 log_drv_label[64];
303 } label_log_drv_t;
304
305 #define SS_TO_VOL 0x58
306
307 #define SET_SURF_DELAY 0x60
308 typedef struct {
309 __u16 delay;
310 __u8 reserved[510];
311 } surf_delay_t;
312
313 #define SET_OVERHEAT_DELAY 0x61
314 typedef struct {
315 __u16 delay;
316 } overhead_delay_t;
317
318 #define SET_MP_DELAY
319 typedef struct {
320 __u16 delay;
321 __u8 reserved[510];
322 } mp_delay_t;
323
324 #define PASSTHRU_A 0x91
325 typedef struct {
326 __u8 target;
327 __u8 bus;
328 __u8 lun;
329 __u32 timeout;
330 __u32 flags;
331 __u8 status;
332 __u8 error;
333 __u8 cdb_len;
334 __u8 sense_error;
335 __u8 sense_key;
336 __u32 sense_info;
337 __u8 sense_code;
338 __u8 sense_qual;
339 __u32 residual;
340 __u8 reserved[4];
341 __u8 cdb[12];
342 } scsi_param_t;
343
344 #define RESUME_BACKGROUND_ACTIVITY 0x99
345 #pragma pack()
346
347 #endif /* ARRAYCMD_H */
348
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